adc1443d NXP Semiconductors, adc1443d Datasheet - Page 23

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adc1443d

Manufacturer Part Number
adc1443d
Description
Dual Channel 14-bit Adc; 125, 160 Or 200 Msps; Jesd204b-compliant Cgvxpress Serial Outputs
Manufacturer
NXP Semiconductors
Datasheet

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ADC1443D_SER
Objective data sheet
11.2.1 Drive modes
11.2 Clock input
The configuration shown in
both cases, the choice of transformer is a compromise between cost and performance.
The ADC1443D series can be driven differentially (LVPECL, LVDS or SINE). It can also
be driven by a single-ended LVCMOS signal connected to either pin CLKP or pin CLKM
(connect the complementary pin to ground using a capacitor). The LVPECL is
recommended for an optimal performance.
Fig 28. Dual transformer configuration (high IF)
Fig 29. LVPECL/LVDS differential clock input
analog
input
All information provided in this document is subject to legal disclaimers.
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
100 nF
Rev. 1 — 28 September 2011
100 nF
Figure 28
LVPECL / LVDS
clock input
100 nF
is recommended for high-frequency applications. In
50 Ω
50 Ω
ADC1443D series
001aan475
CLKM
CLKP
50 Ω
50 Ω
10 Ω
10 Ω
100 nF
001aan666
3.9 pF
© NXP B.V. 2011. All rights reserved.
VCMx
INxM
INxP
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