adc1443d NXP Semiconductors, adc1443d Datasheet - Page 25

• Manufacturer Part Number: adc1443d
• Description: Dual Channel 14-bit Adc; 125, 160 Or 200 Msps; Jesd204b-compliant Cgvxpress Serial Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1443D_SER
Objective data sheet
11.2.2 Equivalent input circuit
11.2.3 Clock input divider
11.2.4 Multi-device synchronization (pins SYSREF, SYSREFN and SYSREFP)
11.3.1 Digital output buffers
11.3 Digital outputs
Figure 32
AC-coupled and the common-mode voltage of the differential input stage is set via internal
5 k resistors.
The ADC1443D contains an input clock divider that divides the incoming clock (clock
frequency f
(see bits CLK_DIV[1:0] in
better jitter performance, leading to a better SNR result once acquisition has been
performed.
The multi-device synchronization can be controlled with a single-ended or a differential
SYSREF signal.
A high level on SYSREF resets the clock divider phase registers. In a multi-device
application and when the clock divider factor is higher than 1, the ADC1443D
synchronization aligns all sampling clock edges (see
The JESD204A/JESD204B standard specifies that both the receiver and the transmitter
must be provided by the same supply if they are connected in DC-coupling.
Fig 32. Equivalent input circuit
CLKM
CLKP
shows the equivalent circuit of the input clock buffer. The input signal must be
clk
) by a factor of 1 to 8. it outputs the sampling clock (sampling frequency f
All information provided in this document is subject to legal disclaimers.
PACKAGE
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 1 — 28 September 2011
Table
ESD
23). This feature delivers a higher clock frequency with
PARASITICS
5 kΩ
5 kΩ
V
cm(clk)
ADC1443D series
Table 8
and
Figure
© NXP B.V. 2011. All rights reserved.
4).
001aan476
25 of 50
s
)