ad1879 Analog Devices, Inc., ad1879 Datasheet - Page 13

• Manufacturer Part Number: ad1879
• Description: High Performance 16-/18-bit Stereo Adcs
• Manufacturer: Analog Devices, Inc.

REV. 0
For slave modes, the word clock (WCK) input has the same
setup time requirement, t
clock (CLOCK at “W” ) as in Figure 16 and a corresponding
hold time, t
the setup edge. The MSB of the DATA output will be delayed
from a falling edge of master clock (CLOCK) by t
Subsequent bits of the DATA output in contrast will be delayed
from a rising edge of master clock (CLOCK) by t
Synchronizing Multiple AD1878/AD1879s
Multiple AD1878/AD1879s can be synchronized either by
making all AD1878/AD1879s serial port slaves or by making
one AD1879 the serial port master and all other AD1879s
slaves. These two options are illustrated in Figure 18.
As a third alternative, it is possible to synchronize multiple mas-
ters all in Master Mode—Word Clock Output mode. See the
“Reset” discussion above in the “Operating Features” section
for timing considerations.
AD1878/AD1879 to DSP56001 Interface
The 18-bit AD1878/AD1879 can be interfaced quite simply to
the DSP56001 Digital Signal Processor. Figure 19 illustrates
one method of connection. In this implementation, the AD1878/
AD1879 is configured to operate in 64-Bit Master Mode With
BCK OUTPUT (64•F
BCK INPUT (64•F
WHLD
DATA OUTPUT
LRCK OUTPUT
DATA OUTPUT
CLOCK INPUT
CLOCK INPUT
LRCK INPUT
WCK INPUT
WCK INPUT
, from the rising edge of CLOCK (W+3) after
S
S
t
)
SET
)
t
DLYCK
PREVIOUS
WSET
t
HLD
B
t
Figure 16. AD1878/AD1879 Master Mode Clock Timing: WCK Input
, to the rising edge of master
SET
B+1 B+2
NEW
L
t
SET
B+3
L+1
Figure 17. AD1878/AD1879 Slave Mode Timing
1
t
HLD
DLYD
DLYD,MSB
ZEROS
.
t
t
ZEROS
DLYD,MSB
WSET
.
–13–
W
t
MSB
t
t
DLYD,MSB
Word Clock Output. Thus, the AD1878/AD1879 is the master
of the serial interface. The AD1878/AD1879 operates indepen-
dently from the DS Ps clock. The DSP56001 serial port is
configured to operate in synchronous mode with the AD1878/
AD1879 connected to its synchronous serial interface (SSI) port.
DLYCK
WSET
W+1 W+2 W+3
Figure 18. Synchronizing Multiple AD1878/AD1879s
MSB
#1
SLAVE MODE
CLK
#2
SLAVE MODE
CLK
#N
SLAVE MODE
CLK
AD1879
AD1879
AD1879
W
W+1 W+2 W+3
MSB–1
t
WHLD
MSB–1
DATA
LRCK
DATA
LRCK
DATA
LRCK
WCK
WCK
WCK
BCK
BCK
BCK
t
t
DLYD
DLYCK
SOURCE
CLOCK
t
WHLD
MSB–2
t
DLYD
MSB–2
t
DLYD
AD1878/AD1879
#1
MASTER MODE
CLK
#2
SLAVE MODE
CLK
#N
SLAVE MODE
CLK
L+30 L+31
AD1879
AD1879
AD1879
t
t
DLYD
DLYCK
t
HLD
DATA
LRCK
DATA
LRCK
DATA
LRCK
WCK
WCK
WCK
BCK
BCK
BCK
SOURCE
CLOCK