ad1879 Analog Devices, Inc., ad1879 Datasheet - Page 12

• Manufacturer Part Number: ad1879
• Description: High Performance 16-/18-bit Stereo Adcs
• Manufacturer: Analog Devices, Inc.

AD1878/AD1879
Also available with the AD1878/AD1879 is a 32-bit frame mode
where the 1879’s 18-bit output is truncated to 16-bit words and
for both parts the output packed “tightly” into two 16-bit fields
in the 32-bit frame as shown in Figure 13. Note that the bit
clock (BCK) and data transmission (DATA) are operating at
one-half the rate as they would in the 64-bit frame modes. The
distinction between master and slave modes still holds in the
32-bit frame modes, though the word clock (WCK) becomes ir-
relevant. If “32-Bit Master Mode With Word Clock Out HI” is
selected, the word clock (WCK) will stay in a constant HI state.
If “32-Bit Master Mode With Word Clock Ignored” is selected,
the word clock pin (WCK) will be three-stated and any input to
it is ignored as meaningless. (However, such an input should be
tied off to HI or LO and not left to float.)
In both 32-bit master modes, the left/right clock (LRCK) will be
an output, indicating the difference between the left word/field
and right word/field. In 32-Bit Slave Mode, the left/right clock
(LRCK) is an input.
Timing Parameters
The AD1878/AD1879 uses its master clock, CLOCK to resyn-
chronize all inputs and outputs. The discussion above presumed
that most timing parameters are relative to the bit clock, BCK.
This is approximately true and provides an accurate model of
the sequence of timing events. However, to be more precise, we
have to specify all setup and hold times relative to CLOCK.
These are illustrated in Figures 15, 16, and 17.
For master modes with word clock (WCK) output, bit clock
(BCK), left/right clock (LRCK), and word clock (WCK) will be
LRCK & WCK OUTPUTS
BCK OUTPUT (64•F
DATA OUTPUT
CLOCK INPUT
Figure 14. AD1878/AD1879 RESET Clock Timing for Synchronizing Master Mode WCK Output
LRCK OUTPUT
CLOCK INPUT
BCK OUTPUT
S
)
t
DLYCK
PREVIOUS
RESET
Figure 15. AD1878/AD1879 Master Mode Clock Timing: WCK Output
NEW
t
RSET
1
FOR SYNCH
MIN 4 CLKS
t
RPLS
t
RHLD
MAX 2 CLKS
FOR SYNCH
MIN 1 CLK
–12–
ZEROS
delayed from a master clock input (CLOCK) rising edge by
t
will be delayed from a falling edge of master clock (CLOCK) by
t
be delayed from a rising edge of master clock (CLOCK) by
t
subsequent bits.)
For master modes with word clock (WCK) inputs, bit clock
(BCK) and left/ right clock (LRCK) will be delayed from a
master clock input (CLOCK) rising edge by t
Figure 16, the same delay as with word clock output modes.
The word clock (WCK) input, however, now has a setup time
requirement, t
at “W”) and a corresponding hold time, t
of the third rising edge of CLOCK (W+3) after the setup edge.
See Figure 16. As in the Master Mode—Word Clock Output
case, the MSB of the DATA output will be delayed from a fall-
ing edge of master clock (CLOCK) by t
bits of the DATA output in contrast will be delayed from a ris-
ing edge of master clock (CLOCK) by t
For slave modes, bit clock (BCK) and left/right clock (LRCK)
will be inputs with setup time, t
requirements to the falling edges of CLOCK as shown in Fig-
ure 17. Note that both edges of BCK and of LRCK have setup
and hold time requirements. Note also that LRCK is setup to
the falling edge of the “L” CLOCK, coincident with the CLOCK
edge to which a falling edge of BCK is setup (B+3). LRCK’s
hold time requirements are relative to the falling edge of the
“L + 31” CLOCK edge.
t
DLYCK
DLYD,MSB
DLYD
t
DLYD,MSB
DLYCK
FOR SYNCH
MIN 4 CLKS
. (The MSB is valid one-half CLOCK period less than the
14
as shown in Figure 15. The MSB of the DATA output
. Subsequent bits of the DATA output in contrast will
WSET
MSB
1
t
, to the rising edge of master clock (CLOCK
DLYCK
t
DLYD
2
15
3
4
MSB–1
126 127 128
SET
16
, and hold time t
DLYD,MSB
DLYD
WHLD
t
t
DLYD
DLYCK
MSB–2
.
DLYCK
, from the rising
. Subsequent
17
as shown in
HLD
REV. 0
,