ad1879 Analog Devices, Inc., ad1879 Datasheet - Page 8

• Manufacturer Part Number: ad1879
• Description: High Performance 16-/18-bit Stereo Adcs
• Manufacturer: Analog Devices, Inc.

AD1878/AD1879
Figure 3. AD1878/AD1879 Recommended Power Condi-
tioning Circuit (If 5 V Supplies Are Not Already Available)
The trim potentiometers shown in Figure 2 connecting the
minus (–) inputs of the driving op amps permit trimming out dc
offset, if desired.
Note that the driving op amp feedback resistors are all slightly
different values. These values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the best overall
THD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. We have done this in the lab by parallel-
ing 100 k trim potentiometers around the 5.49 k and
5.36 k input feedback resistors for the V
that can be found in Figure 2. By trimming gain imbalance, sec-
ond harmonic distortion can always be eliminated. In “Specifi-
cations,” a distinction is drawn between trimmed and untrimmed
signal-to (noise + distortion) and trimmed and untrimmed total
harmonic distortion. The untrimmed specifications are tested to
LEFT
INPUT
RIGHT INPUT
Figure 2. AD1878/AD1879 Recommended Input Structure
AGND
DGND
NE5532 OR OP-275
V
V
V
CC
SS
DD
5.62k
5.62k
5.62k
5.62k
V
V
CC
SS
0.1µF
0.1µF
.1µF
.1µF
0.1µF
100k
5.62k
100k
5.62k
249k
249k
5.62k
249k
249k
5.62k
22µF
22µF
22µF
V
100pF
IN
5.76k
5.36k
100pF
CC
5.49k
100pF
5.90k
100pF
V
IN
GND
7805
V
SS
V
SS
GND
CC
7905
.1µF
.1µF
OUT
.1µF
.1µF
OUT
NE5532 OR
51
NE5532 OR
51
51
51
.01µF
OP-275
+5V DIGITAL
OP-275
NPO
0.1µF
IN
0.1µF
.0047 µF
.0047 µF
.01µF
NPO
plus (+) signals
NPO
NPO
.01µF
NPO
.01µF
NPO
+12V < V
–12V > V
10µF
+5V ANALOG
12
13
16
17
10µF
14
AD1878/79
15
REFR
VINR–
VINR+
VINL+
VINL–
REFL
CC
SS
> – 18V
200
< +18V
200
–5V
ANALOG
10µF
10µF
–8–
the input structure shown in Figure 2. The trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.
The input circuit of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. The recommended architecture shown in
Figure 2 using three inverting op amps per channel provides iso-
lation of the op amp inputs from charge dumped back from the
AD1878/AD1879’s input capacitors when these large capacitors
switch. The performance from a two op amp per channel input
structure is not quite as good as the structure recommended,
but it is close and may be adequate in many applications.
Layout and Decoupling Considerations
Obtaining the best possible performance from a state-of-the-art
data converter like the AD1878/AD1879 requires close atten-
tion to board layout. From extensive experimentation, we have
discovered principles that produce typical values of 103 dB dy-
namic range and 98 dB S/(THD+N) in your system. Schematics
of our AD1878/AD1879 Evaluation Board, which implements
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below in descend-
ing order of importance. The first two pertain to bypassing and
are illustrated in Figure 4.
Figure 4. AD1878/AD1879 Recommended Bypassing and
Oscillator Circuits
• The digital bypassing of the AD1878/AD1879 is the most
• The analog input bypassing is the second most critical item.
10µF
critical item on the board layout. There are two pairs of digi-
tal supply pins of the part, each pair on opposite sides (Pins 5
and 6 and Pins 22 and 23). The user should tie a bypass ca-
pacitor set (0.1 F ceramic and 10 F tantalum) on EACH
pair of supply pins as close to the pins as possible. The traces
between these package pins and the capacitors should be as
short and as wide as possible. This will prevent digital supply
current transients from being inductively transmitted to the
inputs of the part.
Use 0.01 F NPO ceramic capacitors from each input pin to
the analog ground plane, with a clear ground path from the
bypass capacitor to the AGND pin on the same side of the
package (Pins 10 and 18). The trace between this package
pin and the capacitor should be as short and as wide as pos-
sible. A 0.0047 F NPO ceramic capacitor should be placed
ANALOG +5V
AV
AV
–5V
9
SS
8
SS
ANALOG
1 AV
2 AV
10µF
–5V
ANALOG
21
SS
DD
20
10µF
1 AV
2
AD1878/ 79
DIGITAL
19
DV
5
+5V
ANALOG
DD
DD
0.1µF
10µF
+5V
1 AGND
DGND
10
6
18
23
DGND DV
AGND
0.1µF
10µF
DIGITAL
+5V
CLKIN
22
DD
26
+5V DIGITAL
OSCILLATOR
REV. 0
0.1µF