ad1879 Analog Devices, Inc., ad1879 Datasheet - Page 10

• Manufacturer Part Number: ad1879
• Description: High Performance 16-/18-bit Stereo Adcs
• Manufacturer: Analog Devices, Inc.

AD1878/AD1879
In the “slave modes,” the bit clock (BCK), the word clock
(WCK), and the left/right clock (LRCK) are user-supplied in-
puts. Note that, for performance reasons, the AD1878/AD1879
does not support asynchronous operation; these clocks must be
externally derived from the master clock (CLOCK). The func-
tional sequence of the signals in the slave modes is identical to
the master modes with word clock input, and they share the
same sequence timing diagrams.
In 64-Bit Master Mode with Word Clock Output, the 16-/18-bit
words are right-justified in 32-bit fields as shown in Figures 7
and 8. The WCK output goes HI approximately with the falling
edge of the BCK output, indicating that the MSB on DATA will
be externally valid at the next BCK rising edge. The LRCK out-
put discriminates the left from the right output fields.
In 64-bit frame modes with word clock (WCK) is an input, the
16-/18-bit words can be placed in user-defined locations within
32-bit fields. This is true in both master and slave modes. The
Figure 9. AD1878/AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Transitions HI Before 16th BCK
(AD1878)/14th BCK (AD1879) (Master Mode or Slave Mode)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
LRCK
DATA
LRCK
DATA
WCK
WCK
DATA OUTPUT
DATA OUTPUT
BCK
BCK
WCK INPUT
PREVIOUS DATA
PREVIOUS DATA
LRCK I/O
BCK I/O
AD1879
AD1878
LSB
LSB
32
32
Figure 8. AD1878 64-Bit Frame Output Timing with WCK as Output (Master Mode Only)
1
1
ZEROS
ZEROS
Figure 7. AD1879 64-Bit Output Timing with WCK as Output (Master Mode Only)
32
2
2
ZEROS
ZEROS
1
3
3
N–1
14
14
LEFT DATA
LEFT DATA
MSB
MSB
MSB MSB–1 MSB–2 MSB–3
N
15
15
MSB–1
MSB–1
N+1
LEFT DATA
16
16
LEFT DATA
MSB MSB–1
17
LSB–3
LSB–1
17
N+14
18
18
LSB-2
N+15 N+16
LSB
LSB–1
LSB–3
LSB–3
29
29
LSB–2
LSB–2 LSB–1
N+17
LSB
30
30
LSB–1
31
31
–10–
31
LSB
LSB
32
ZEROS
ZEROS
32
options are illustrated in Figures 9, 10, 11, and 12. For all op-
tions, the first occurrence in a 32-bit field when the word clock
(WCK) is HI on a bit clock (BCK) falling edge will cause the
beginning of data transmission. The MSB on DATA will be
valid at the next BCK rising edge. Again, the LRCK output dis-
criminates the left from the right output fields.
Figure 9 illustrates the general case for 64-bit frame modes with
word clock input where the MSB is valid on the rising edge of
the Nth bit clock (BCK). Figures 10 and 11 illustrate the limits.
If WCK is still LO at the falling edge of the 14th bit clock (BCK)
for the AD1879 or 16th bit clock (BCK) for the AD1878, then the
MSB of the current word will be output anyway, valid at the ris-
ing edge of the 15th bit clock (BCK) in the field for the AD1879,
17th for the AD1878. This limit insures that all 16/18 bits will
be output within the current field. The effect is to right-justify
the data.
32
1
1
ZEROS
1
ZEROS
2
2
N–1
3
3
RIGHT DATA
RIGHT DATA
MSB MSB–1
MSB MSB–1
N
14
14
N+1
MSB
15
15
LSB–3 LSB-2 LSB–1
LSB–1
MSB–1 MSB–2 MSB–3
N+14
RIGHT DATA
16
16
RIGHT DATA
MSB MSB–1
N+15 N+16
LSB
17
17
18
18
N+17
LSB
LSB–3
LSB–3
29
29
LSB–2
LSB–2 LSB–1
30
31
30
LSB–1
ZEROS
ZEROS
31
32
31
LSB
LSB
32
32
1
REV. 0
1
1