ad1879 Analog Devices, Inc., ad1879 Datasheet - Page 9

• Manufacturer Part Number: ad1879
• Description: High Performance 16-/18-bit Stereo Adcs
• Manufacturer: Analog Devices, Inc.

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• For best performance, do not use a socket with the AD1878/
• The AD1878/AD1879 should be placed on a split ground
• Each reference pin (14 and 15) should be bypassed with a
• Wherever possible, minimize the capacitive load on digital
How to Extend SNR
A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use mul-
tiple AD1879 channels in parallel with a common analog input.
(The same technique would work with the AD1878. However,
this would be of little value since using a single AD1879 would
Figure 5. AD1878/AD1879 Recommended Ground Plane
between each set of input pins (12 to 13, and 17 to 16) to
complete the input bypassing. This input bypassing mini-
mizes the RF transmission and reception capability of the
AD1878/AD1879 inputs.
AD1879. If you must socket the part, use pin clips to keep
the part flush with the board, thus keeping bypassing as
close to the chip as possible.
plane as illustrated in Figure 5. The digital ground plane
should be placed under the top end of the package and the
analog ground plane should be placed under the bottom end
of the package as shown in Figure 5. The split should be be-
tween Pins 7 and 8 and between Pins 21 and 22. The
ground planes should be tied together at one spot under-
neath the center of the package. This ground plane tech-
nique also minimizes RF transmission and reception.
resistor and a capacitor. One end of the resistor should be
placed as close to the package pin as possible, and the trace
to it from the reference pin should be as short and as wide as
possible. Keep this trace away from input pin traces! Cou-
pling between input and reference traces will cause second
harmonic distortion. The resistor is used to reduce the high
frequency coupling into the references from the board.
outputs of the part. This will reduce the digital spike cur-
rents drawn from the digital supply pins.
AV
AV
DGND
AGND
VINR–
VINR+
LRCK
REFR
DV
64/32
APD
BCK
SS
SS
NC
S0
DD
1
2
10
12
13
14
11
2
8
9
1
3
4
5
6
7
ANALOG GROUND
DIGITAL GROUND
PLANE
PLANE
17
28
26
25
24
20
19
18
16
15
27
23
22
21
RESET
WCK
DATA
CLK
DGND
DV
AV
REFL
S1
AV
AV
AGND
VINL–
VINL+
DD
SS
DD
DD
1
2
1
–9–
be more effective.) This technique makes use of the fact that the
noise in independent modulator channels is uncorrelated. Thus
every doubling of the number of AD1879 channels used will im-
prove system dynamic range by 3 dB. The digital outputs from
the corresponding decimator channels have to be arithmetically
averaged to obtain the improved results in the correct data for-
mat. A digital processor, either general-purpose or DSP, can
easily perform the averaging operation.
Shown below in Figure 6 is a circuit for obtaining a 3 dB im-
provement in dynamic range by using both channels of a single
AD1879 with a mono input. The minus (–) output from the in-
put buffer is sent to both right and left minus AD1879 inputs;
the plus (+) output from the input buffer is sent to both right
and left plus AD1879 inputs. A stereo implementation would
require using two AD1879s and using the full recommended in-
put structure shown above in Figure 2. Note that a single digital
processor would likely be able to handle the averaging require-
ments for both left and right channels.
DIGITAL INTERFACE
Modes of Operation
The AD1878/AD1879’s flexible serial output port produces
data in twos-complement, MSB-first format. Output signals are
to TTL/CMOS logic levels. The port is configured by pin selec-
tions. The AD1879 can operate in either master or slave modes.
Each 16-/18-bit output word of a stereo pair can be formatted
within a 32-bit field as right-justified, as I
user-selected positions. The two 32-bit fields constitute a 64-bit
frame (64-bit mode). The output can also be truncated to 16
bits and formatted in a 16-bit field with two 16-bit fields in a
32-bit frame (32-bit mode).
The various mode options are pin-programmed with the S0
Mode Select Pin (3), the S1 Mode Select Pin (25), and the
64/32 Bit Rate Select Pin (4). The function of these pins is
summarized:
Serial Port Operation Mode
64-Bit Master Mode—Word Clock Output
64-Bit Master Mode—Word Clock Input
64-Bit Slave Mode
Reserved
32-Bit Master Mode—Word Clock Out HI
32-Bit Master Mode—Word Clock Ignored
32-Bit Slave Mode
Reserved
Serial Port Data Timing Sequences
In the “master modes,” the bit clock (BCK) and left/right clock
(LRCK) are always outputs, generated internally in the AD1878/
AD1879 from the master clock (CLOCK) input. The word
clock (WCK) may either be an internally generated output or a
user-supplied input, depending on the pin-programmed mode
selected.
0.200
0.125
Figure 6. Increasing Dynamic Range by Using Two
AD1879 Channels
(6.35)
0.250
MAX
(5.05)
(3.18)
PIN
0.022
0.014
1
(0.558)
(0.356)
2
8
1
0.625
0.600
0.015
0.008
(2.54)
0.100
BSC
1.565
1.380
(15.87)
(15.24)
(0.381)
(0.204)
(39.70)
(35.10)
AD1878/AD1879
0.195
0.125
2
(4.95)
(3.18)
0.070
S-compatible, or at
MAX
(1.77)
64/32
1
1
1
1
0
0
0
0
15
14
0.580
0.485
0.060
0.015
SEATING
PLANE
0.150
(3.81)
MIN
(14.73)
(12.32)
S0
0
1
1
0
0
1
1
0
(1.52)
(0.38)
S1
0
0
1
1
0
0
1
1