kad5512hp Kenet Inc., kad5512hp Datasheet - Page 21

• Manufacturer Part Number: kad5512hp
• Description: High Performance 12-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

this document. Additionally, within a defined register
there may be certain bits or bit combinations that
are reserved. Undefined registers and undefined val-
ues within defined registers are reserved and should
not be selected. Setting any reserved register or
value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization
for the data transfer. By default, all data is presented
on the serial data input/output (SDIO) pin in three-
wire mode. The state of the SDIO pin is set automati-
cally in the communication protocol (described be-
low). A dedicated serial data output pin (SDO) can
be activated by setting 0x00[7] high to allow opera-
tion in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5512HP functioning as a
KAD5512HP
Figure 37. Instruction/Address Phase
Figure 49. N-Byte Transfer
Figure 38. 2-Byte Transfer
slave. Multiple slave devices can interface to a single
master in four-wire mode only, since the SDIO output
of an unaddressed device is asserted in three wire
mode.
The chip-select bar (CSB) pin determines when a
slave device is being addressed. Multiple slave de-
vices can be written to concurrently, but only one
slave device can be read from at a given time
(again, only in four-wire mode). If multiple slave de-
vices are selected for reading at the same time, the
results will be indeterminate.
The communication protocol begins with an instruc-
tion/address phase. The first rising SCLK edge follow-
ing a high to low transition on CSB determines the
beginning of the two-byte instruction/address com-
mand. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be
changed by setting 0x00[6] high. Figures 35 and 36
show the appropriate bit ordering for the MSB-first
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