kad5512hp Kenet Inc., kad5512hp Datasheet - Page 24

• Manufacturer Part Number: kad5512hp
• Description: High Performance 12-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

Address 0x71: phase_slip
When using the clock divider, it’s not possible to deter-
mine the synchronization of the incoming and divided
clock phases. This is particularly important when multi-
ple ADCs are used in a time-interleaved system. The
phase slip feature allows the rising edge of the divided
clock to be advanced by one input clock cycle, as
shown in Figures 40 and 41. This register is self-clearing.
Address 0x72: clock_divide
The KAD5512HP has a selectable clock divider that
can be set to divide by four, two or one (no division).
By default, the tri-level CLKDIV pin selects the divisor
(refer to Clock Input section). This functionality can be
overridden and controlled through the SPI, as shown
in Table 12. This register is not changed by a Soft Reset.
Figure 41. Phase Slip: CLK÷4 Mode, f
KAD5512HP
Figure 40. Phase Slip: CLK÷2 Mode, f
Value
000
001
010
100
Clock Divider
Divide by 1
Divide by 2
Divide by 4
Pin Control
0x72[2:0]
CLOCK
CLOCK
=1000MHz
=500MHz
Address 0x73: output_mode_A
The output_mode_A register controls the physical out-
put format of the data, as well as the logical coding.
The KAD5512HP can present output data in two physi-
cal formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects
the mode and drive level (refer to Digital Outputs sec-
tion). This functionality can be overridden and con-
trolled through the SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default,
the tri-level OUTFMT pin selects the data format (refer
to Data Format section). This functionality can be over-
ridden and controlled through the SPI, as shown in Ta-
ble 14.
This register is not changed by a Soft Reset.
Address 0x74: output_mode_B
Address 0x75: config_status
Bit 6
Bit 4
Internal clock signals are generated by a delay-
locked loop (DLL), which has a finite operating range.
Table 15 shows the allowable sample rate ranges for
the slow and fast settings.
DLL Range
This bit sets the DLL operating range to fast
(default) or slow.
DDR Enable
Setting this bit enables Double Data-Rate
mode.
Table 12. Clock Divider Selection
Table 14. Output Format Control
Table 13. Output Mode Control
Value
Value
000
001
010
100
000
001
010
100
Two’s Complement
Output Format
Offset Binary
Gray Code
Pin Control
Pin Control
0x93[7:5]
LVDS 2mA
LVDS 3mA
0x93[2:0]
LVCMOS
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