kad5510p Kenet Inc., kad5510p Datasheet - Page 17

• Manufacturer Part Number: kad5510p
• Description: Low Power 10-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input matched to
VCM. The value of the shunt resistor should be determined based on the
desired load impedance. The differential input resistance of the
KAD5510P is 1000Ω.
The SHA design uses a switched capacitor input stage
(see Figure 40 on page 27), which creates current spikes when
the sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle before
the next sampling point. Lower source impedance will result in
faster settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier, as shown in Figure 27, can be used in
applications that require DC-coupling. In this configuration, the
amplifier will typically dominate the achievable SNR and
distortion performance.
The current spikes from the SHA will try to force the analog input
pins toward ground. In cases where the input pins are biased with
more than 50 ohms in series from VCM care must be taken to
make sure the input common mode range is not violated. The
provided ICM value (250µA/MHz * 250MHz = 625µA at
FIGURE 25. TRANSFORMER INPUT FOR GENERAL PURPOSE
FIGURE 26. TRANSMISSION-LINE TRANSFORMER INPUT FOR
1000pF
49.9
0.22µF
1000pF
1000pF
Ω
FIGURE 27. DIFFERENTIAL AMPLIFIER INPUT
ADT1-1WT
69.8
69.8
ADTL1-12
APPLICATIONS
HIGH IF APPLICATIONS
Ω
100
100
Ω
Ω
Ω
ADTL1-12
ADT1-1WT
348
348
17
CM
Ω
Ω
0.1µF
0.1µF
25
25
0.1µF
Ω
Ω
217
Ω
VCM
KAD5512P
KAD5512P
KAD5512P
VCM
KAD5510P
VCM
250MSPS) may be used to calculate the expected voltage drop
across any series resistance.
VCM Output
The VCM output is buffered with a series output impedance of
20Ω. It can easily drive a typical ADC driver’s 10kΩ common
mode control pin. If an external buffer is not used the voltage
drop across the internal 20Ω impedance must be considered
when calculating the expected DC bias voltage at the analog
input pins.
Clock Input
The clock input circuit is a differential pair (see Figure 41).
Driving these inputs with a high level (up to 1.8V
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 28. A duty
cycle range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. This allows
the use of the Phase Slip feature, which enables synchronization
of multiple ADCs.
The clock divider can be controlled through the SPI port. Details on this
are contained in “Serial Peripheral Interface” on page 21.
A delay-locked loop (DLL) generates internal clock signals for
various stages within the charge pipeline. If the frequency of the
input clock changes, the DLL may take up to 52µs to regain lock
at 250MSPS. The lock time is inversely proportional to the
sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t
illustrated in Figure 29.
SNR
200pF
=
20 log
FIGURE 28. RECOMMENDED CLOCK DRIVE
10
TC4-1W
⎛
⎝
------------------ -
2πf
1
IN
J
) and SNR is shown in Equation 1 and is
t
J
⎞
⎠
1000pF
200pF
200pF
200O
P-P
Ω
on each
January 3, 2011
CLKP
CLKN
FN7693.1
(EQ. 1)