kad5510p Kenet Inc., kad5510p Datasheet - Page 18

• Manufacturer Part Number: kad5510p
• Description: Low Power 10-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 1. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the reference
charges used in the successive approximation operations. The full-scale
range of each A/D is proportional to the reference voltage. The voltage
reference is internally bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible or
CMOS double data rate (DDR) modes. When CLKOUT is low the
MSB and all odd logical bits are output, while on the high phase
the LSB and all even logical bits are presented. Figures 1 and 1
show the timing relationships for LVDS/CMOS DDR modes.
The KAD5510P is only offered in the 48-QFN package with five
LVDS data output pin pairs. It only supports outputs in DDR
mode.
LVDS output drive current can be set to a nominal 3mA or a
power-saving 2mA. The lower current setting can be used in
designs where the receiver is in close physical proximity to the
ADC. The applicability of this setting is dependent upon the PCB
layout, therefore the user should experiment to determine if
performance degradation is observed.
The output mode and LVDS drive current are selected via SPI
registers. Details are contained in “Serial Peripheral Interface” on
page 21.
Care should be taken when using the DDR CMOS outputs at clock
rates greater than 200MHz. Series termination resistors close to
the ADC should drive short traces with minimum parasitic
loading to assure adequate signal integrity.
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
100
95
90
85
80
75
70
65
60
55
50
1
tj = 100ps
FIGURE 29. SNR vs CLOCK JITTER
INPUT FREQUENCY (MHz)
10
tj = 10ps
18
tj = 1ps
tj = 0.1ps
100
10 BITS
14 BITS
12 BITS
KAD5510P
1000
Over Range Indicator
The over range (OR) bit is asserted when the output code reaches
positive full-scale (e.g. 0xFFF in offset binary mode). The output
code does not wrap around during an over-range condition. The OR
bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5510P is primarily dependent
on the sample rate and the output modes: LVDS vs. CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation is approximately constant in
LVDS mode, but linearly related to the clock frequency in CMOS
mode. Figures 33 and 34 illustrate these relationships.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to less than 95mW and recovers to normal operation in
approximately 1µs. Sleep mode reduces power dissipation to less
than 6mW but requires approximately 1ms to recover from a sleep
command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during sleep,
requiring a user to wait 150µs max after CSB is asserted
(brought low) prior to writing ‘001x’ to SPI Register 25. The
device would be fully powered up, in normal mode 1ms after this
command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep mode, the
150µs CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation increases
by ~ 15mW in this case. The 1ms wake-up time after the write of a
‘001x’ to register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional SPI
activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 1.
January 3, 2011
FN7693.1