kad5510p Kenet Inc., kad5510p Datasheet - Page 28

• Manufacturer Part Number: kad5510p
• Description: Low Power 10-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

Equivalent Circuits
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be used to
evaluate any of the KADxxxxx ADC family. The platform consists
of a FPGA based data capture motherboard and a family of ADC
daughtercards. This USB based platform allows a user to quickly
evaluate the ADC’s performance at a user’s specific application
frequency requirements. More information is available at:
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
PCB Layout Example
For an example application circuit and PCB layout, please refer to
the evaluation board documentation provided in the web product
folder at:
http://www.intersil.com/products/partsearch.asp?txtprodnr=ka
d5510p
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and terminations
as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
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0.535V
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FIGURE 46. VCM_OUT OUTPUT
KAD5510P
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance. Care should be taken when using the
DDR CMOS outputs at clock rates greater than 200MHz. Series
termination resistors close to the ADC should drive short traces
with minimum parasitic loading to assure adequate signal
integrity
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO) which will not
be operated do not require connection to ensure optimal ADC
performance. These inputs can be left floating if they are not
used. The SDO output must be connected to OVDD with a 4.7kΩ
resistor or the ADC will not exit the reset state. Tri-level inputs
(NAPSLP) accept a floating input as a valid state, and therefore
should be biased according to the desired functionality.
General PowerPAD Design
Considerations
Figure 47 is a generic illustration of how to use vias to remove
heat from a QFN package with an exposed thermal pad. A
specific example can be found in the evaluation board PCB
layout previously referenced.
AVDD
FIGURE 47. PCB VIA PATTERN
VCM
January 3, 2011
FN7693.1