dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 303

• Manufacturer Part Number: dsp56800e
• Description: 16-bit Digital Signal Controller Core
• Manufacturer: Freescale Semiconductor, Inc

10.3.8.2
The time when interrupt arbitration is allowed to resume is calculated as follows:
10.3.8.3
Some special cases increase interrupt latency. Section 9.3.4, “Non-Interruptible Instruction Sequences,” on
page 9-10 documents instruction sequences that are not interruptible. Such sequences increase latency.
Figure 10-11 demonstrates such a case. When the instruction n1 is a 1-word conditional branch instruction,
and when the condition evaluates to false, the two instructions immediately following the Bcc, n2 and n3,
are non-interruptible.
The STOP instruction places the core into the stop processing state, where interrupts are not recognized.
The WAIT instruction places the core into the wait processing state. An enabled interrupt brings the core
out of this low-power state.
The REP instruction and the instruction that it repeats are not interruptible. Instead, these two instructions
are treated as a single 2-word instruction, regardless of the number of times that the second instruction is
repeated. Instruction fetches are suspended and are re-activated only after the repeat loop is finished (see
Figure 10-12 on page 10-24). During the execution of n2 in Figure 10-12, no interrupts will be serviced.
When the loop finally completes, instruction fetches are re-initiated and pending interrupts can be serviced.
Freescale Semiconductor
Pipeline
Int Arbitr
Int Req
Stage
OP2
EX2
AG
EX
P1
P2
ID
IF
Re-enable = Execution time of instruction n1
Figure 10-11. Interrupt Latency Calculation—Non-Interruptible Instructions
Re-Enabling Interrupt Arbitration
Cases That Increase Interrupt Latency
n1 n2 n3 n4
1
n1 n2 n3
2
+ 4 clock cycles (1 for arbitration and 3 NOPs forced into pipeline)
+ 3 clock cycles (first 3 cycles executing the JSR instruction)
+ wait states when the JSR instruction pushes the PC and SR to the stack
+ wait states due to program fetches of n3, n4, and ii0–ii2
n1 n2
3
i
bcc bcc bcc n2
4
i
Sampled by the Arbiter
bcc bcc bcc
Interrupt Requests
n5
n4
n3
5
bcc bcc bcc
n6
n5
n4
6
bcc bcc bcc
n7
n6
n5
7
bcc bcc bcc
n8
n7
n6
n3
n2
8
Instruction Pipeline
n8
n7
n2
ii0
—
n3
9
10 11
n8
n3
n2
ii1
ii0
—
—
Instruction Cycle
n3
n2
ii1
ii1
ii0
—
—
—
12 13 14
ii1
ii1
ii1
jsr
—
—
—
n3
ii2
ii1
ii1
jsr
jsr
—
—
—
Pipeline During Interrupt Processing
jsr
ii3
ii2
ii1
jsr
jsr
—
—
15 16 17
ii3
jsr
jsr
jsr
jsr
ii4
ii2
—
ii4
ii3
ii2
jsr
jsr
jsr
jsr
•
ii4
ii3
ii2
jsr
jsr
jsr
Reaches Decode
•
•
First Instruction
18 19 20 21 22
jsr
ii4
ii3
ii2
jsr
•
•
•
jsr
ii4
ii3
ii2
•
•
•
•
ii4
ii3
ii2
•
•
•
•
•
ii4
ii3
•
•
•
•
•
•
10-23
ii4
•
•
•
•
•
•
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