dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 461
dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
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DEC.W
Operation:
D – 1 → D (one parallel move)
D – 1 → D (no parallel move)
Description: Decrement a 16-bit destination by one. If the destination is an accumulator, only the EXT and MSP
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
A Before Execution
A2
0
portions of the accumulator are used and the LSP remains unchanged. The condition codes are calcu-
lated based on the 16-bit result (or on the 20-bit result for accumulators).
This instruction is typically used when integer data is processed.
DEC.W
Prior to execution, the 36-bit A accumulator contains the value $0:0001:0033. Execution of the
DEC.W instruction decrements by one the upper 20 bits of the A accumulator and sets the zero bit in
the CCR. A new value is read in parallel and stored in register X0; the address register R2 is post-in-
cremented.
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
C
When the destination is one of the four accumulators, condition code calculations follow the rules for
20-bit arithmetic; otherwise, the rules for 16-bit arithmetic apply.
LF
15
— Set if limiting (parallel move) or overflow has occurred in result
— Set if the extension portion of the result is in use
— Set if result is unnormalized
— Set if bit MSB of the result is set
— Set if the result is zero (20 MSB for accumulator destinations)
— Set if overflow has occurred in result
— Set if a carry (or borrow) occurs from bit 15 of the result (bit 35 for accumulators)
0001
P4
14
A1
A
13
P3
SR
P2
12
MR
P1
11
X:(R2)+,X0
0033
0300
A0
P0
10
Decrement Word
Instruction Set Details
I1
9
Assembler Syntax:
DEC.W
DEC.W
I0
8
; Decr the 20 MSBs of A, update R2,X0
SZ
7
A After Execution
6
L
A2
0
5
E
D
D
U
4
CCR
0000
A1
N
3
(one parallel move)
(no parallel move)
SR
2
Z
V
1
0033
0314
C
0
A0
DEC.W
A-117
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