dsp56800e Freescale Semiconductor, Inc, dsp56800e Datasheet - Page 375
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dsp56800e
Manufacturer Part Number
dsp56800e
Description
16-bit Digital Signal Controller Core
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800E.pdf
(706 pages)
- Current page: 375 of 706
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AND.W
Operation:
S • D → D
S • D[31:16] → D[31:16]
where • denotes the logical AND operator
Description: Perform a logical AND operation on the source operand (S) and the destination operand (D), and store
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
X0
6
the result in the destination. This instruction is a 16-bit operation. If the destination is a 36-bit accumu-
lator, the operation is performed on the source and bits 31–16 of the accumulator. The remaining bits
of the destination accumulator are not affected. If the source is an immediate 5-bit constant, it is first
zero extended to form a 32-bit operand. The result is not affected by the state of the saturation bit (SA).
This instruction is used for the logical AND of two registers or of a register and a small immediate
value. The ANDC instruction is appropriate for performing an AND operation on a 16-bit immediate
value and a register or memory location.
AND.W
Prior to execution, the 16-bit X0 register contains the value $7F00, and the 36-bit A accumulator con-
tains the value $6:1234:5678. The AND.W X0,A instruction performs a logical AND operation on the
16-bit value in the X0 register and on bits 31–16 of the A accumulator (A1), and it stores the 36-bit
result in the A accumulator. Bits 35–32 in the A2 register and bits 15–0 in the A0 register are not af-
fected by this instruction.
N
Z
V
LF
15
— Set if bit 31 of accumulator result or MSB of register result is set
— Set if bits 31–16 of accumulator result or all bits of register result are zero
— Always cleared
1234
7F00
P4
14
A1
X0,A
13
P3
SR
(no parallel move)
(no parallel move)
P2
12
MR
P1
11
5678
030F
A0
P0
10
Instruction Set Details
; logically AND X0 with A1
I1
AND Word
9
Assembler Syntax:
AND.W
AND.W
I0
8
SZ
7
After Execution
6
L
A2
X0
6
5
E
S,D
S,D
U
4
CCR
7F00
1200
A1
N
3
(no parallel move)
(no parallel move)
SR
2
Z
V
1
5678
0301
C
0
A0
AND.W
A-31
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