z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet
z893232yfsc
Related parts for z893232yfsc
z893232yfsc Summary of contents
Page 1
FEATURES DSP ROM OTP DSP RAM Device (K Words) (K Words) Z89323 8 Z89373 8 Z89393 64* * External Operating Temperature Ranges +70 C (Standard) – +85 C (Extended) 4.5- to 5.5-Volt Operating Range DSP ...
Page 2
GENERAL DESCRIPTION (Continued) The Z893X3 DSP family is 100 percent source and object- code compatible with the existing Z89321/371/391 devices, providing users, who can benefit from increased integration and reduced system cost, an easy migration path from one DSP product ...
Page 3
PIN DESCRIPTION EXT3/P03 EXT4/P04 VSS EXT5/P05 EXT6/P06 EXT7/P07 INT1/P21 EXT8/P08 EXT9/P09 VSS EXT10/P010 Figure 2. 44-Pin PLCC Z89323/373 Pin Configuration Table 1. 44-Pin PLCC Z89323/373 Pin Description No. Symbol Function 1 P20/INT0 Port 2 0/Interrupt 0 2 EXT12/P012 Ext Data ...
Page 4
PIN DESCRIPTION (Continued EXT3/P03 12 EXT4/P04 13 VSS 14 VDD EXT5/P05 15 16 SOUT/P13 EXT6/P06 17 18 SS/P14 19 EXT7/P07 SK/P15 20 P27 21 EXT8/P08 22 EXT9/P09 23 24 VSS 25 EXT10/P010 VSS ...
Page 5
Table 2. 68-Pin PLCC Z89323/373 Pin Description No. Symbol Function 1 P12/SIN Port 1 2/Serial Input 2 P20/INT0 Port 2 0/Interrupt 0 3 EXT12/P012 Ext Data 12/Port EXT13/P013 Ext Data 13/Port ...
Page 6
PIN DESCRIPTION (Continued) EXT3/P03 EXT4/P04 VSS EXT5/P05 EXT6/P06 EXT7/P07 INT1/P21 EXT8/P08 EXT9/P09 VSS EXT10/P010 Figure 4. 44-Pin QFP Z89323/373 Pin Configuration Table 3. 44-Pin QFP Z89323/373 Pin Description No. Symbol Function 1 EXT3/P03 Ext Data 3/Port EXT4/P04 ...
Page 7
NC 2 EXT15/P015 3 /EXTEN EXT3/P03 6 P32 EXT4/P04 7 8 VSS 9 VCC 10 EXT5/P05 11 P13/SOUT 12 EXT6/P06 13 P14/SS 14 EXT7/P07 15 P15/SK 16 P27 17 EXT8/P08 18 EXT9/P09 19 VSS 20 P33 ...
Page 8
PIN DESCRIPTION (Continued) Table 4a. 80-Pin QFP Z89323/373 Pin Description No. Symbol Function Connection 2 EXT15/P015 Ext Data 15/Port XTEN Ext Enable Connection 5 EXT3/P03 Ext Data ...
Page 9
EXT3/P03 3 PA8 4 EXT4/P04 5 PA9 6 VSS 7 VDD 8 EXT5/P05 9 PA10 10 SOUT/P13 11 EXT6/P06 PA11 12 13 SS/P14 14 EXT7/P07 15 SK/P15 16 P27 17 PA12 18 EXT8/P08 19 PA13 20 EXT9/P09 ...
Page 10
PIN DESCRIPTION (Continued) Table 4. 100-Pin QFP Z89393 Pin Description No. Symbol Function XTEN EXT Enabl e 2 EXT3/P03 Ext Data 3/Port Program Address 8 4 EXT4/P04 Ext Data 4/Port 0 ...
Page 11
PIN FUNCTIONS CLKO-CLKI Clock (output/input). These pins act as the clock circuit input and output. EXT15-EXT0 External Data Bus (input/output). These pins act as the data bus for user-defined outside registers, such as an ADC or DAC. The pins are ...
Page 12
PIN FUNCTIONS (Continued) VAHI and VALO. Analog to Digital reference voltages. /PAZ Tri-state Program Bus. This pin enables the Program Address bus for emulation purposes. ADDRESS SPACE Program Memory. Programs Kwords can be masked into internal ...
Page 13
REGISTERS The internal registers of the Z89323/373/393 are defined below: Register Register Definition P Output of Multiplier, 24-bit X X Multiplier Input, 16-bit Y Y Multiplier Input, 16-bit A Accumulator, 24-bit SR Status Register, 16-bit Pn:b Six Ram Address Pointers, ...
Page 14
REGISTERS (Continued) The Status Register The status register can always be read in its entirety. S15- S10 are set/reset by hardware and can only be read by software. S9-S0 control hardware looping and can be written by software (Table 8). ...
Page 15
EXT Register Assignments The EXT registers support is extended in the Z893X3 family: In addition seven external registers, there are 28 internal registers on the EXT bus. There are 16 different pages of EXT registers. The same ...
Page 16
EXT Register Assignments (Continued) Ext 7 Reg D15 D14 D13 D12 D11 Interrupt Status Bits When read, these bits provide interrupt information to identify the source for INT2, or when the DSP works in Pending Interrupt mode, to warn the ...
Page 17
Bank15/EXT3 Reg D15 D14 D13 D12 D11 D10 DS95DSP0101 Q4/ Figure 8a. Bank 15/EXT3 Register Z89323/373/393 16 ...
Page 18
FUNCTIONAL DESCRIPTION Analog to Digital Converter (ADC) The ADC is an 8-bit half flash converter that uses two reference resistor ladders for its upper 4 bits (Most Significant Bits) and lower 4 bits (Least Significant Bits) conversion. Two reference voltage ...
Page 19
Integrated Logic 4-Channel Multiplexer DS95DSP0101 Q4/ INT0 Timer Start Converter A/D Prescaler VREF Flash Sample A/D and Converter Hold AGND Channel Select Figure 9. ADC Architecture Z89323/373/393 16-B D ...
Page 20
FUNCTIONAL DESCRIPTION (Continued) Bank 13/Ext 0 (low byte Figure 10. ADCTL Register (Low Byte) Prescaler Values (bits (Crystal divided by ...
Page 21
START (bits 9, 8) ADST1 ADST0 Mode 0 0 Conversion starts when this register is written Conversion starts on a rising edge INT1 input pin Conversion starts when Timer 2 times out Conversion starts ...
Page 22
FUNCTIONAL DESCRIPTION (Continued Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
Page 23
TIMER/COUNTERS The Z89323/373/393 has two 16-bit Timer/Counters that can be independently configured to operate in various modes. Each is implemented as a 16-bit Load Register (TMLR) and a 16-bit down counter (TMR). Timer/Counter inputs can be selected from among UI0 ...
Page 24
TIMER/COUNTERS (Continued) Timer Modes The Timer modes can be categorized as input modes and output modes. In input modes, the Timer/Counter is used for input signals only. In output modes, a selected output pin is driven Timer/Counter is ...
Page 25
Bank 13/EXT1 (Timer0) or Bank 14/EXT1 (Timer1) Timer Control Register (TCTL DS95DSP0101 Q4/ ...
Page 26
TIMER/COUNTERS (Continued) Timer Load Register (TMLR) This 16-bit Register holds a value that is reloaded into timer upon timer under flow. 15 Timer Reload Value Timer Prescaler Load Register (TPLR) The 16-bit TPLR Register holds the prescaler reload value in ...
Page 27
Prescaler Operation The Timer/Counter Clock (TMCLK) is generated by the output of the prescaler. The Prescaler is an 8-bit down counter, TPR, followed by a divide-by-two flip-flop that generates a 50 percent duty cycle output clock TMCLK. The Prescaler’s input ...
Page 28
TIMER/COUNTERS (Continued) 16-Bit General-Purpose Timer/Counter T2 The 16-bit timer/counter is available for general-purpose use. When the counter counts down to the zero state, the timer 2 load register loads into timer 2, and if timer 2 interrupt is enabled, an ...
Page 29
Programmable I/O (Port 0) When the appropriate bit is set in the Port 1 control register, Port 0 acts as a 16-bit programmable, bidirectional, CMOS- compatible port. Each of the 16 lines can be independently programmed as an input ...
Page 30
Programmable I/O (Port 1) When the appropriate bit is set in the Port 1 control register, Port 1 acts as an 8-bit programmable, bi-directional, CMOS-compatible port. Each of the eight lines can be independently programmed as an input or ...
Page 31
Programmable I/O (Port 2) Port 8-bit programmable, bidirectional, CMOS- compatible port. Each of the eight lines can be independently programmed as an input or an output or globally as an open-drain output. Port 2 can also ...
Page 32
Serial Peripheral Interface Serial Peripheral Interface (SPI). The Z893X3 incorporates a serial peripheral interface for communication with other microcontrollers and peripherals. The SPI includes features such as Master/Slave selection. The SPI consists of two registers; SPI Control Register (SCON), SPI ...
Page 33
When the communication between the master and slave is complete, the SS goes High. Unless disconnected, for every bit that is transferred into the slave through the SIN pin, a bit is transferred out through the SOUT pin on the ...
Page 34
CLOCK Circuits The clock generator includes Phase-Locked Loop (PLL) circuit to enable use of low frequency crystal. The benefits of using low frequency crystal are low system cost, low power consumption and low EMI. The PLL circuit can be bypass ...
Page 35
Power Down The Z893X3 supports different levels of power-down modes to minimize device power consumption. The lowest power consumption is at STOP Clock Mode when the Oscillator is turned off (clock modes 2 and 4 when there is no external ...
Page 36
Interrupt Controller There are eight different interrupt sources (when all of them are enabled). Bits [3:0] of the Interrupt Allocation Register defines which interrupt source will have the highest priority and will be allocated into IINT0 (Internal INT0). Bits[7:0] of ...
Page 37
FUNCTIONAL DESCRIPTION Instruction Timing. Most instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. A multiplication or multiplication/accumulate instruction requires a single cycle. Specific instruction cycle times are ...
Page 38
FUNCTIONAL DESCRIPTION (Continued) Hardware Stack. A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The Call instruction pushes PC+2 onto the stack, and the RET instruction pops the contents of the stack to ...
Page 39
RAM ADDRESSING The address of the RAM is specified in one of three ways (Figure 22): %FF RAM Pointers P0:0 P1:0 256 x 16-Bit %37 P2:0 @P1:0 %37 %00 @@P1:0 Figure 31. RAM, ROM, and Pointer Architecture Register Indirect Pn:b ...
Page 40
The register pointer is specified by the first and second bits in the source/destination field and the modification is specified by the third and fourth bits according to the following table: D3-D0 Meaning 00xx NOP No Operation 01xx + 1 ...
Page 41
INSTRUCTION FORMAT Table 13. Registers Source/Destination 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D15 D14 D13 D12 D11 D10 D9 Note: Source/Destination fields can specify either register or RAM address in ...
Page 42
INSTRUCTION FORMAT (Continued) D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 ...
Page 43
D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 DS95DSP0101 Q4/ ...
Page 44
ADDRESSING MODES This section discusses the syntax of the addressing modes supported by the DSP assembler. Symbolic Name < > < > (Points to RAM) <hwregs> <accind> (Points to Program ...
Page 45
There are eight distinct addressing modes for data transfer. <pregs>, <hwregs> These two modes are used for simple loads to and from registers within the chip, such as loading to the Accumulator, or loading from a pointer register. The names ...
Page 46
INSTRUCTION DESCRIPTIONS Inst. Description Synopsis Absolute Value ABS[<cc>,]<src> Addition ADD<dest>,<src> Bitwise AND AND<dest>,<src> CALL Subroutine call CALL [<cc>,]<address> Clear carry flag ...
Page 47
Inst. Description Synopsis L D Load destination LD<dest>,<src> with source MLD Multiply MLD<srcl>,<srcl>[,<bank switch> Multiply and add MPYA <srcl>,<src2>[,<bank switch>] DS95DSP0101 Q4/ Operands A,<hwregs> A,<dregs> ...
Page 48
INSTRUCTION DESCRIPTIONS (Continued) Inst. Description Synopsis Multiply and MPYS<src1>,<src2>[,<bank switch>] <hwregs>,<regind> subtract Negate NEG <cc>, operation Bitwise OR OR <dest>,<src> Pop ...
Page 49
Inst. Description Synopsis Set C flag Set IE flag SLL Shift left SLL logical Set OP flag ...
Page 50
ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage (*) CC T Storage Temp STG T Oper Ambient Temp A Notes: * Voltage on all pins with respect to GND. † See Ordering Information. STANDARD TEST CONDITIONS The characteristics listed below ...
Page 51
AC ELECTRICAL CHARACTERISTICS (20 MHZ 10 +70 C, unless otherwise noted Symbol Parameter Clock TCY Clock Cycle Time Tr Clock Rise Time Tf Clock Fall Time CPW Clock Pulse Width ...
Page 52
AC ELECTRICAL CHARACTERISTICS (20 MHZ) (Continued 10 +70 C, unless otherwise noted Analog to Digital Resolution Integral Non-Linearity Differential Non-Linearity Zero Error Supply Range Power Dissipation, No ...
Page 53
AC ELECTRICAL CHARACTERISTICS (10 MHZ 10 +70 C, unless otherwise noted Symbol Parameter Clock TCY Clock Cycle Time Tr Clock Rise Time Tf Clock Fall Time CPW Clock Pulse Width ...
Page 54
TIMING DIAGRAMS CLOCK DSVALID /DS EASET Valid Address Out EA(2:0) RD//WR EXT(15:0) CLOCK WSET WAIT /DS EA(2:0) RD//WR EXT(15: TCY DSHOLD EAHOLD RDHOLD RDSET Data In Figure 42. ...
Page 55
CLOCK DSVALID /DS EASET EA(2:0) EASET RD//WR EXT(15:0) CLOCK WAIT /DS EA(2:0) RD//WR EXT(15:0) DS95DSP0101 Q4/ TCY DSHOLD EAHOLD Valid Address Out EAHOLD WRHOLD WRVALID Data In Figure 44. ...
Page 56
TIMING DIAGRAMS (Continued) CLOCK INT 0,1,2 PROGRAM Fetch N –1 ADDRESS EXECUTE CLOCK HHOLD HSET HALT TCY INTSET INTWidth Fetch N Fetch N +1 Fetch Int_Addr Execute N ...
Page 57
CLOCK RSET /RESET INTERNAL RESET EXECUTE Cycle 0 RD//WR /DS UO0-1 EA0-2 EXT0-15 PA0-15 RAM/ REGISTERS CLOCK PAVALID PROGRAM ADDRESS PROGRAM DATA Figure 49. External Program Memory Port Timing DS95DSP0101 Q4/ ...
Page 58
PACKAGE INFORMATION 44-Pin PLCC Package Diagram 68-Pin PLCC Package Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
Page 59
DS95DSP0101 Q4/ 44-Pin QFP Package Diagram 80-Pin QFP Package Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS 59 ...
Page 60
PACKAGE INFORMATION (Continued 100-Pin QFP Package Diagram Z89323/373/393 16 IGITAL IGNAL ROCESSORS DS95DSP0101 Q4/95 ...
Page 61
... Z893232XVSC Z893731XVSC Z893232XVEC 44-Pin PQFP 44-Pin PQFP Z8932320FSC Z8937316FSC Z8932320FEC 80-Pin PQFP 80-Pin PQFP Z893232YFSC Z893731YFSC Z893232YFEC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package V = Plastic PLCC F = Plastic QFP Temperature + – +85 C ...