z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 27

• Manufacturer Part Number: z893232yfsc
• Description: 16-bit Digital Signal Processors
• Manufacturer: ZiLOG Semiconductor

Prescaler Operation
The Timer/Counter Clock (TMCLK) is generated by the
output of the prescaler. The Prescaler is an 8-bit down
counter, TPR, followed by a divide-by-two flip-flop that
generates a 50 percent duty cycle output clock TMCLK.
The Prescaler’s input clock is the system clock, CLKIN,
divided by two. Thus, the maximum prescaler output
frequency is 1/4 of the system clock frequency.
Once the prescaler counter is loaded, it decrements at its
clocked frequency and generates an output to the divide-
by-two flip-flop. When the count reaches 0, the counter is
reloaded from the lower 8 bits of TPLR Register.
DS95DSP0101 Q4/95
UIO
UI1
TMCLK
15
M
U
X
IP
(System Clock)
14
Figure 17. Counter/Timer Block Diagram
Clock
Figure 16. Prescaler Block Diagram
15
15
Zeros
P R E L I M I N A R Y
8 7
TMLR Register
8-Bit Counter
TMR Register
16-Bit Counter
Reload Value
Prescaler
TPR
The 8-bit prescaler counter is loaded with value in TPLR
Register field [7:0] in one of three ways:
1. When 8-bit prescaler counter, TPR,
2. By writing to TPR Register.
3. When companion Timer/Counter TMR is reloaded
decrements to zero.
upon under flow from its TMLR Register, or
retriggered by writing directly to TMR Register.
0
S
E
L
TPLR
Register
U00
U01
DIV
by 2
0
0
16-B
IT
D
TMCLK
IGITAL
S
IGNAL
Z89323/373/393
P
ROCESSORS
27