z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 36

• Manufacturer Part Number: z893232yfsc
• Description: 16-bit Digital Signal Processors
• Manufacturer: ZiLOG Semiconductor

Interrupt Controller
There are eight different interrupt sources (when all of them
are enabled). Bits [3:0] of the Interrupt Allocation Register
defines which interrupt source will have the highest priority
and will be allocated into IINT0 (Internal INT0). Bits[7:0] of
the Interrupt Allocation Register defines which interrupt
source will have the second highest priority and will be
allocated into IINT1 (Internal INT1). Bits[15:8] are enable
36
Note: An Interrupt that is not selected as a source to IINT0, IINT1 or IINT2 is disabled.
Bank 15/Ext 6 Reg
D15 D14 D13
D12
D11
D10
D9
Figure 28. Interrupt Allocation Register
D8
P R E L I M I N A R Y
D7
D6
D5
D4
bits for specific interrupt sources. All the enabled interrupts
which are not already allocated into IINT0 or IINT1 are
allocated into IINT2. When interrupt happen on IINT2 then
IINT2 interrupt routine is reading the Interrupt Status Register
(EXT7 in all the Banks) to determine which interrupt occurred
and decides on the relative priority. The Interrupt Status
Register can be used for polling interrupts mode.
D3
D2
D1
D0
IINT0 Source
IINT1 Source
IINT2 Interrupt Sources
0000 : A/D Finish
0010 : Timer0
0100 : Timer2
0110 : INT1 H/W
1000 – 1111 : IINT0 Disabled
0000 : A/D Finish
0010 : Timer0
0100 : Timer2
0110 : INT1 H/W
1000 – 1111 : IINT1 Disabled
Bit 8 = A/D Finish
Bit 9 = SPI
Bit 10 = Timer0
Bit 11 = Timer1
Bit 12 = Timer2
Bit 13 = INT0 H/W 1
Bit 14 = INT1 H/W 1
Bit 15 = INT2 H/W 1
16-B
DS95DSP0101 Q4/95
IT
D
IGITAL
Interrupt
Enable
1
1
1
1
1
S
0001 : SPI
0011 : Timer1
0101 : INT0 H/W
0111 : INT2 H/W
0001 : SPI
0011 : Timer1
0101 : INT0 H/W
0111 : INT2 H/W
IGNAL
Z89323/373/393
Interrupt
Disable
P
ROCESSORS
0
0
0
0
0
0
0
0