z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 35

• Manufacturer Part Number: z893232yfsc
• Description: 16-bit Digital Signal Processors
• Manufacturer: ZiLOG Semiconductor

Power Down
The Z893X3 supports different levels of power-down modes
to minimize device power consumption. The lowest power
consumption is at STOP Clock Mode when the Oscillator
is turned off (clock modes 2 and 4 when there is no external
clock.) The highest power consumption is when the Z893X3
in Normal mode (Clock Mode 0) and there is medium
power consumption mode .The SLOW Clock Mode is when
the DSP is running with 32 kHz clock (Crystal Clock Modes
1 and 3) and disabling all the peripherals which are not
needed in this mode.
Slow Mode
The SLOW mode reduce the chip power consumption by
using the 32 kHz clock (Clock Mode 3) of the crystal as a
DSP clock and disabling in software all the unnecessary
peripherals.
Clock Mode 1 also uses the 32 kHz clock, but in this mode
the VCO is still running to enable fast switching (wake up)
to the high frequency.
DS95DSP0101 Q4/95
Bank 15/Ext 5 Reg
D15 D14 D13
D12
D11
D10
D9
D8
P R E L I M I N A R Y
D7
Figure 27. PLL Register
D6
D5
D4
Stop Mode
The STOP mode provides the lowest possible device
standby current.
oscillator and internal system clock are turned off.
In Clock Mode 2 the Oscillator is running while the system
clock is turned off to enable fast switching (wake up) to the
high frequency.
STOP mode is exited when the recovery source as defined
in Bank4/EXT5[6:5] is toggled to the recovery defined
level. In case of Clock Mode 2 the program resumes
operation starting from the next instruction after the stop
instruction. In case of Clock Mode 4, the program resumes
operation starting
executing operations similar to the Power-On Reset
sequence of operations.
D3
Programmable PLL Divider Register
VCO Frequency = Bits 15-8 * 8 * Crystal Frequency (32 kHz)
39 (9.984 MHz) < Bits 15-8 < 158 (40.448 MHz)
D2
D1
D0
In this mode of operation the on chip
from the reset vector address after
STOP_OSC
STOP_VCO
BYPASS_PLL
DSP (System) Clock Source
Recovery Source
STOP Recovery Level
0 : Oscillator Running
1 : Stop Oscillator
0 : VCO Running
1 : Stop VCO
0 : Clock Source is VCO
1 : Clock Source is Oscillator
00 : VCO Clock
01 : VCO Clock Divided by 2
10 : VCO Clock Divided by 4
11 : Twice the Crystal Frequency
00 : POR (Power-On Reset) or
01 : POR or Port 1, Bit 4 (SS)
10 : POR or Port 1, Bit 6 (UI0)
11 : POR or Port 2, Bit 0 or
0 : Low (Default setting after reset.)
1 : High
16-B
Port 2, Bit 0 (INT0)
Port 1, Bit 4 or Port 1, Bit 6
IT
D
IGITAL
S
IGNAL
Z89323/373/393
P
ROCESSORS
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