z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 31

• Manufacturer Part Number: z893232yfsc
• Description: 16-bit Digital Signal Processors
• Manufacturer: ZiLOG Semiconductor

8-Bit Programmable I/O (Port 2)
Port 2 is an 8-bit programmable, bidirectional, CMOS-
compatible port. Each of the eight lines can be
independently programmed as an input or an output or
globally as an open-drain output. Port 2 can also be
8-Bit Programmable I/O (Port 3)
Port 3 is an additional I/O port featured only in the 80-pin
PQFP package. P3[3:0] are inputs and P3[7:4] are outputs.
The purpose of this additional port is to serve applications
that need more than 32 I/O pins. Port 3 enables the
user to support up to 40 I/O pins. Port 3 is not
DS95DSP0101 Q4/95
Port.Bit
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Bank 15/Ext 2 Reg
D15 D14 D13
*Note:
The user should always program this bit to be 0.
IF (Condition Explanation)
Bank15/Ext2(9)=1 (Enable External Interrupt Source INT0)
Bank15/Ext1(4)=1 (Enable External Interrupt Source INT1)
Bank13/Ext1(6-5)=10 or Bank14/Ext1(6-5)=10 (UO0 Enable)
Bank13/Ext1(6-5)=11 or Bank14/Ext1(6-5)=11 (UO0 Enable)
Bank15/Ext2(14)=1 (UO2 Enable)
Bank15/Ext2(13)=1 (Timer2 Clock is UI2)
D12
D11
D10
D9
D8
Table 11. Port 2 Bit Function Selection
D7
Figure 22. Bank15/EXT2 Register
P R E L I M I N A R Y
D6
D5
D4
D3
programmed to provide special I/O functions. When Port 2
acts as programmable I/O, Bank0/EXT5 (MSB) acts as the
data I/O register. Bank15/EXT2 serves as Port 2 control
register.
supported in the 100-pin ICE chip PQFP package,
therefore this port is not supported in the Z893x3
emulator,
recommended in cases when the other I/O ports
can support the I/O requirements.
D2
D1
D0
and
Port 2 I/O Directions
1 : Enable Port 3
0 : Disable Port 3 (default)
1 : Enable External Interrupt Source INT0
0 : Disable External Interrupt Source INT0 (default)
1 : Port 2 Outputs Open-Drain
0 : Port 2 Outputs Push-Pull (default)
1 : Enable Timer 2
0 : Disable Timer 2 (default)
1 : Enable Timer 2 Counting
0 : Disable Timer 2 Counting (default)
1 : Timer 2 Clock is UI2
0 : Timer 2 Clock is System Clock/2 (default)
1 : UO2 Enabled (P24)
0 : UO2 Disabled (default)
Timer2 Test Mode*
0 : Normal Operation (default)
1 : Factory Test Mode
1 : Output
0 : Input (default)
UI2
Then
INT0
INT1
UO0
UO1
UO2
P26
P27
use
of
16-B
this
IT
D
IGITAL
Else
P20
P21
P22
P23
P24
P25
P26
P27
port
S
IGNAL
Z89323/373/393
P
is
ROCESSORS
not
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