z893232yfsc ZiLOG Semiconductor, z893232yfsc Datasheet - Page 47

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z893232yfsc

Manufacturer Part Number
z893232yfsc
Description
16-bit Digital Signal Processors
Manufacturer
ZiLOG Semiconductor
Datasheet
Inst.
L D
MLD
M P Y A
DS95DSP0101 Q4/95
Description
Load destination
with source
Multiply
Multiply and add
Synopsis
LD<dest>,<src>
MLD<srcl>,<srcl>[,<bank switch>]
MPYA <srcl>,<src2>[,<bank switch>]
P R E L I M I N A R Y
Operands
A,<hwregs>
A,<dregs>
A,<pregs>
A,<regind>
A,<memi n d>
A,<direct>
<direct>,A
<dregs>,<hwregs>
<pregs>,<si m m>
<pregs>,<hwregs>
<regind>,<limm>
<regind>,<hwregs>
<hwregs>,<pregs>
<hwregs>,<dregs>
<hwregs>,<limm>
<hwregs>,<accind>
<hwregs>,<memi n d>
<hwregs>,<regind>
<hwregs>,<hwregs>
Note: When <dest> is <hwregs>, <dest> cannot be P.
Note: When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be EXTn
Note: When <src> is <accind> <dest> cannot be A.
<hwregs>,<regind>
<hwregs>,<regind>,<bank switch> 1
<regind>,<regind>
<regind>,<regind>,<bank switch>
Note: If src1 is <regind> it must be a bank 1 register. Src2’s <regind must be
Note: <hwregs> for src1 cannot be X.
Note: For the operands <hwregs>, <regind> the <band switch> defaults to OFF.
<hwregs>,<regind>
<hwregs>,<regind>,<bank switch> 1
<regind>,<regind>
<regind>,<regind>,<bank switch>
Note: If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be
Note: <hwregs> for src1 cannot be X.
Note: For the operands <hwregs>, <regind> the <bank switch> defaults to OFF.
if <src> is EXTn, <dest> cannot be X if <src> is X, <dest> cannot be SR
if <src> is SR.
a bank 0 register.
For the operands <regind>, the <bank switch> defaults to ON.
a bank 0 register.
For the operands <regind>, the <bank switch> defaults to ON.
W o r d s Cycles Examples
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
16-B
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
2
3
3
1
1
1
1
1
1
1
IT
D
LD A,X
LD A,D0:0
LD A,P0:1
LD A,@P1:1
LD A,@D0:0
LD A,124
LD 124,A
LD D0:0,EXT7
LD P1:1,#%FA
LD P1:1,EXT1
LD@P1:1,#1234
LD @P1:1+,X
LD Y,P0:0
LD SR,D0:0
LD X,@A
LD Y,@D0:0
LD A,@P0:0–LOOP
LD X,EXT6
MLD A,@P0:0+LOOP
MLD A,@P1:0,OFF
MLD @P1:1,@P2:0
MLD @P0:1,@P1:0,ON
MPYA A,@P0:0
MPYA A,@P1:0,OFF
MPYA @P1:1,@P2:0
MPYA@P0:1,@P1:0,ON
IGITAL
LD PC,#%1234
S
IGNAL
Z89323/373/393
P
ROCESSORS
47

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