ksz8051mlli Micrel Semiconductor, ksz8051mlli Datasheet - Page 13

• Manufacturer Part Number: ksz8051mlli
• Description: 10base-t/100base-tx Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Strapping Options – KSZ8051MLL
Note:
1.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to the
unintended high/low states. In this case, external pull-ups (4.7K) or pull-downs (1.0K) should be added on these PHY
strap-in pins to ensure the intended values are strapped-in correctly.
July 2010
22
21
20
27
41
40
29
43
23
42
28
32
Pin Number
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
PHYAD2
PHYAD1
PHYAD0
CONFIG2
CONFIG1
CONFIG0
ISO
SPEED
DUPLEX
NWAYEN
B-CAST_OFF
NAND_Tree#
Pin Name
Ipd/O
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipd/O
Ipu/Opu
Type
(1)
Pin Function
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
The default PHY Address is 00001.
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
ISOLATE mode
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
SPEED mode
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
DUPLEX mode
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
Broadcast Off – for PHY Address 0
At the de-assertion of reset, this pin value is latched by the chip.
NAND Tree Mode
At the de-assertion of reset, this pin value is latched by the chip.
Nway Auto-Negotiation Enable
CONFIG[2:0]
000
110
001 – 101, 111
Pull-up = Enable
Pull-down (default) = Disable
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
Pull-up (default) = Disable
Pull-down = Enable
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
13
Mode
MII (default)
MII Back-to-Back
Reserved – not used
M9999-071210-1.0
KSZ8051MLL