ksz8051mlli Micrel Semiconductor, ksz8051mlli Datasheet - Page 20

• Manufacturer Part Number: ksz8051mlli
• Description: 10base-t/100base-tx Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
MII Management (MIIM) Interface
The KSZ8051MLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface enables upper-layer device, like a MAC processor, to monitor and control the state
of the KSZ8051MLL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
As the default, the KSZ8051MLL supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is
defined per the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MLL device, or write to
multiple KSZ8051MLL devices simultaneously.
Optionally, PHY address 0 can be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin
28) or software (register 16h, bit 9), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8051MLL device.
Table 3 shows the MII Management frame format for the KSZ8051MLL.
Interrupt (INTRP)
INTRP (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8051MLL PHY register. Register 1Bh, bits [15:8] are the interrupt control bits to enable and disable the
conditions for asserting the INTRP signal. Register 1Bh, bits [7:0] are the interrupt status bits to indicate which interrupt
conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Register 1Fh, bit 9 sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8051MLL control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
July 2010
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Read
Write
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows the external controller
to communicate with one or more PHY devices.
A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined per the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See “Register Map” section
for details.
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Table 3. MII Management Frame Format – for KSZ8051MLL
Read/Write
OP Code
10
01
Bits [4:0]
Address
00AAA
00AAA
PHY
20
Bits [4:0]
Address
RRRRR
RRRRR
REG
TA
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Bits [15:0]
Data
M9999-071210-1.0
KSZ8051MLL
Idle
Z
Z