ksz8051mlli Micrel Semiconductor, ksz8051mlli Datasheet - Page 9

• Manufacturer Part Number: ksz8051mlli
• Description: 10base-t/100base-tx Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Pin Description – KSZ8051MLL
July 2010
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin Number
GND
GND
GND
VDD_1.2
NC
NC
VDDA_3.3
NC
RXM
RXP
TXM
TXP
GND
XO
XI
REXT
GND
MDIO
MDC
RXD3 /
PHYAD0
RXD2 /
PHYAD1
RXD1 /
PHYAD2
RXD0 /
DUPLEX
GND
VDDIO
Pin Name
Gnd
Gnd
Gnd
P
-
-
P
-
I/O
I/O
I/O
I/O
Gnd
O
I
I
Gnd
I/O
I
Ipu/O
Ipd/O
Ipd/O
Ipu/O
Gnd
P
Type
(1)
Pin Function
Ground
Ground
Ground
1.2V core V
Decouple with 2.2uF and 0.1uF capacitors to ground, and join with pin 31 by power
trace or plane.
No connect
No connect
3.3V analog V
No connect
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Ground
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
Set PHY transmit output current
Connect a 6.49KΩ resistor to ground on this pin.
Ground
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain like, and requires an external 1.0KΩ
pull-up resistor.
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
MII Mode:
Config Mode:
MII Mode:
Config Mode:
MII Mode:
Config Mode:
MII Mode:
Config Mode:
Ground
3.3V, 2.5V or 1.8V digital V
DD
DD
(power supplied by KSZ8051MLL)
The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset. See Strapping Options section for details.
The pull-up/pull-down value is latched as PHYADDR[1] at the
de-assertion of reset. See Strapping Options section for details.
The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See Strapping Options section for details.
The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See Strapping Options section for details.
MII Receive Data Output[3]
MII Receive Data Output[2]
MII Receive Data Output[1]
MII Receive Data Output[0]
9
DD
(2)
(2)
(2)
(2)
/
/
/
/
M9999-071210-1.0
KSZ8051MLL