ksz8051mlli Micrel Semiconductor, ksz8051mlli Datasheet - Page 17

• Manufacturer Part Number: ksz8051mlli
• Description: 10base-t/100base-tx Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
MII Signal Definition
Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
RXDV transitions synchronously with respect to RXC.
July 2010
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MII Signal Name
TXC
TXEN
TXD[3:0]
RXC
RXDV
RXD[3:0]
RXER
CRS
COL
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
(with respect to PHY,
KSZ8051MLL signal)
Direction
Output
Output
Output
Output
Output
Output
Output
Input
Input
Table 1. MII Signal Definition
(with respect to MAC)
Input, or (not required)
Direction
Output
Output
Input
Input
Input
Input
Input
Input
17
Receive Data Valid
Collision Detection
Description
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Transmit Enable
Transmit Data [3:0]
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
Receive Data [3:0]
Receive Error
Carrier Sense
M9999-071210-1.0
KSZ8051MLL