mc68hc908lb8 Freescale Semiconductor, Inc, mc68hc908lb8 Datasheet - Page 64

• Manufacturer Part Number: mc68hc908lb8
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Computer Operating Properly (COP) Module
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
2
configuration register 1. With a 2
produce bus speed of 4 MHz gives a COP timeout period of 16.383 ms. Writing any value to location
$FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12–5 of
the SIM counter.
A COP reset pulls the RST pin low for 32 × BUSCLKX4 cycles and sets the COP bit in the reset status
register (RSR). See
6.3 I/O Signals
The following paragraphs describe the signals shown in
6.3.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the crystal frequency, the
internal oscillator frequency, or the RC oscillator frequency.
6.3.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see
counter and clears bits 12–5 of the SIM counter. Reading the COP control register returns the low byte of
the reset vector.
6.3.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after power
up.
6.3.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
64
18
– 2
4
or 2
13
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
– 2
4
BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
17.7.2 SIM Reset Status
18
– 2
MC68HC908LB8 Data Sheet, Rev. 1
4
BUSCLKX4 cycle overflow option, using the internal clock to
Register.
NOTE
NOTE
Figure
6.4 COP Control
6-1.
Register) clears the COP
Freescale Semiconductor