mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 107

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mc68hc908kx8

Manufacturer Part Number
mc68hc908kx8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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DDRA4–DDRA0 — Data Direction Register A Bits
Figure 11-4
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
11.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the five port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically disabled when a port bit’s DDRA is
configured for output mode.
Freescale Semiconductor
These read/write bits control port A data direction. Reset clears DDRA4–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
1. I/O pin pulled up to V
2. Writing affects data register, but does not affect input.
PTAPUE
X = Don’t care
Hi-Z = High impedance
Bit
shows the port A I/O logic.
X
1
0
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
DDRA
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Bit
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
0
0
1
PTAPUEx
PTA
DD
Bit
X
X
X
by internal pulllup device
Table 11-1. Port A Pin Functions
Input, V
RESET
Input, Hi-Z
Figure 11-4. Port A I/O Circuit
I/O Pin
Output
Mode
V
INTERNAL
PULLUP
DEVICE
DD
DD
(1)
Table 11-1
NOTE
Accesses to DDRA
DDRAx
PTAx
DDRA4–DDRA0
DDRA4–DDRA0
DDRA4–DDRA0
Read/Write
summarizes the operation of the port A pins.
PTA4–PTA0
Read
Pin
Pin
Accesses to PTA
PTA4–PTA0
PTA4–PTA0
PTA4–PTA0
PTAx
Write
(2)
(3)
Port A
107

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