mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 80

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator Module (ICG)
7.4.4 Quantization Error in DCO Output
The digitally controlled oscillator (DCO) is comprised of three major sub-blocks:
Each of these blocks affects the clock period of the internal clock (ICLK). Since these blocks are controlled
by the digital loop filter (DLF) outputs DDIV and DSTG, the output of the DCO can only change in
quantized steps as the DLF increments or decrements its output. The following subsections describe how
each block will affect the output frequency.
7.4.4.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock
(ICLK), whose clock period is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]).
Because of the digital nature of the DCO, the clock period of ICLK will change in quantized steps. This
will create a clock period difference, or quantization error (Q-ERR) from one cycle to the next. Over
several cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202% to
0.368%. The dependence of this error on the DDIV[3:0] value and the number of cycles the error is
measured over is shown in
7.4.4.2 Binary Weighted Divider
The binary weighted divider divides the output of the ring oscillator by a power of 2, specified by the DCO
divider control bits (DDIV[3:0]). DDIV maximizes at %1001 (values of %1010 through %1111 are
interpreted as %1001), which corresponds to a divide by 512. When DDIV is %0000, the ring oscillator’s
output is divided by 1. Incrementing DDIV by one will double the period; decrementing DDIV will halve the
period. The DLF cannot directly increment or decrement DDIV; DDIV is only incremented or decremented
when an addition or subtraction to DSTG carries or borrows.
80
•
•
•
Binary weighted divider
Variable-delay ring oscillator
Ring oscillator fine-adjust circuit
%0101 – %1001 (max)
%0000 (min)
%0000 (min)
%0000 (min)
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
DDIV[3:0]
%0001
%0001
%0001
%0010
%0010
%0010
%0011
%0011
%0100
%0100
Table
Table 7-3. Quantization Error in ICLK
7-3.
ICLK Cycles
≥ 16
≥ 32
≥ 8
≥ 4
≥ 2
≥ 1
1
4
1
4
1
4
1
1
Bus Cycles
NA
≥ 8
NA
≥ 4
NA
≥ 2
NA
≥ 1
NA
≥ 1
≥ 1
1
1
1
0.202% – 0.368%
0.202% – 0.368%
0.403% – 0.735%
0.202% – 0.368%
0.202% – 0.368%
0.403% – 0.735%
0.202% – 0.368%
0.202% – 0.368%
0.806% – 1.47%
0.806% – 1.47%
6.45% – 11.8%
1.61% – 2.94%
3.23% – 5.88%
1.61% – 2.94%
τ
ICLK
Q-ERR
Freescale Semiconductor