mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 163

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.8 I/O Registers
These I/O registers control and monitor operation of the TIM:
15.8.1 TIM Status and Control Register
The TIM status and control register (TSC):
TOF — TIM Overflow Flag Bit
TOIE — TIM Overflow Interrupt Enable Bit
TSTOP — TIM Stop Bit
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This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete,
then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect.
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter has reached modulo value.
0 = TIM counter has not reached modulo value.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
1 = TIM counter stopped
0 = TIM counter active
TIM status and control register (TSC)
TIM control registers (TCNTH and TCNTL)
TIM counter modulo registers (TMODH and TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H and TCH0L, TCH1H and TCH1L)
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address: $0020
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
Reset:
Read:
Write:
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
Bit 7
TOF
Figure 15-5. TIM Status and Control Register (TSC)
0
0
= Unimplemented
TOIE
6
0
TSTOP
5
1
NOTE
TRST
4
0
0
3
0
0
PS2
2
0
PS1
1
0
Bit 0
PS0
0
I/O Registers
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