mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 117

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

break character and then transmits at least one 1. The automatic 1 at the end of a break character
guarantees the recognition of the start bit of the next character.
12.4.2.3 Break Characters
The SCI recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0
where the stop bit should be. Receiving a break character has these effects on SCI registers:
12.4.2.4 Idle Characters
An idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the
M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
12.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at 1.
See
12.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
Freescale Semiconductor
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12.7.1 SCI Control Register
Sets the framing error bit (FE) in SCS1
Sets the SCI receiver full bit (SCRF) in SCS1
Clears the SCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or reception-in-progress flag (RPF) bits
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
When queueing an idle character, return the TE bit to 1 before the stop bit
of the current character shifts out to the TxD pin. Setting TE after the stop
bit appears on TxD causes data previously written to the SCDR to be lost.
A good time to toggle the TE bit for a queued idle character is when the
SCTE bit becomes set and just before writing the next byte to the SCDR.
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
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Functional Description
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