mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 110

• Manufacturer Part Number: mc68hc08az60
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
MC68HC08AZ60 — Rev 1.0
110
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
frequency, f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f
The VCO’s output clock, CGMVCLK, running at a frequency f
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency f
Programming the PLL for more information.
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode, as
described in
of the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
condition based on this comparison.
Freescale Semiconductor, Inc.
For More Information On This Product,
Clock Generator Module (CGM)
RDV
NOM
Go to: www.freescale.com
Acquisition and Tracking Modes
. The circuit determines the mode of the PLL and the lock
RDV
, (4.9152 MHz) times a linear factor L or (L)f
= f
RCLK
.
VRS
is equal to the nominal center-of-range
RCLK
, and is fed to the PLL through a
on page 111. The value
VDV
= f
VCLK
VCLK
NOM
MOTOROLA
VRS
/N. See
.
, is fed
.
6-cgm