mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 94

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mc68hc08az60

Manufacturer Part Number
mc68hc08az60
Description
M68hc08 Family Of 8-bit Microcontroller Units Mcus
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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System Integration Module (SIM)
Program Exception Control
Interrupts
MC68HC08AZ60 — Rev 1.0
94
INTERRUPT
MODULE
I BIT
R/W
IDB
IAB
DUMMY
DUMMY
Normal, sequential program execution can be changed in three different
ways:
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
10
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared), see
9.
SP
PC – 1[7:0]
Freescale Semiconductor, Inc.
shows interrupt recovery timing.
For More Information On This Product,
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
SP – 1
System Integration Module (SIM)
PC – 1[15:8]
Figure 8
Go to: www.freescale.com
SP – 2
.
X
Interrupt Entry
SP – 3
Figure 8
A
SP – 4
CCR
shows interrupt entry timing.
VECT H
V DATA H
VECT L
V DATA L
START ADDR
OPCODE
MOTOROLA
Figure
Figure
12-sim

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