mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 14

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

DDR and DDR2 SDRAM
Table 10
6
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8349EA. Note that DDR SDRAM is GV
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
14
Input hold time for POR configuration signals with respect to
negation of HRESET
Time for the MPC8349EA to turn off POR configuration signals
with respect to the assertion of HRESET
Time for the MPC8349EA to turn on POR configuration signals
with respect to the negation of HRESET
Notes:
1. t
2. t
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual .
PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual .
results in the minimum and an 8:1 ratio results in the maximum.
PCI_SYNC_IN
CLKIN
DDR and DDR2 SDRAM
is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
lists the PLL and DLL lock times.
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware
Specifications. See
Document,” for silicon revision level determination.
Parameter/Condition
Parameter/Condition
Table 9. RESET Initialization Timing Specifications (continued)
Section 23.1, “Part Numbers Fully Addressed by This
Table 10. PLL and DLL Lock Times
DD
(typ) = 2.5 V and DDR2 SDRAM is GV
NOTE
7680
Section 19, “Clocking.”
Min
Min
—
—
0
1
122,880
Max
Max
100
—
—
4
csb_clk cycles
t
PCI_SYNC_IN
Freescale Semiconductor
Unit
Unit
ns
ns
μs
DD
(typ) = 1.8 V.
Notes
Notes
1, 3
1, 2
—
—
3