mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 79

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

21.2
Each PLL gets power through independent power supply pins (AV
level should always equal to V
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 41
21.3
Due to large address and data buses and high operating frequencies, the MPC8349EA can generate
transient power surges and high frequency noise in its power supply, especially while driving large
capacitive loads. This noise must be prevented from reaching other components in the MPC8349EA
system, and the MPC8349EA itself requires a clean, tightly regulated source of power. Therefore, the
system designer should place at least one decoupling capacitor at each V
of the MPC8349EA. These capacitors should receive their power from separate V
LV
placed directly under the device using a standard escape pattern. Others can surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, distribute several bulk storage capacitors around the PCB, feeding the V
and LV
Freescale Semiconductor
DD
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
, and GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be
DD
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in
PLL Power Supply Filtering
Decoupling Recommendations
shows the PLL power supply filter circuit.
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
DD
pin being supplied. It should be possible to route directly from the capacitors to the AV
V
DD
DD
Figure 41. PLL Power Supply Filter Circuit
10 Ω
, and preferably these voltages are derived directly from V
2.2 µF
Section 19.2, “Core PLL Configuration.”
GND
Low ESL Surface Mount Capacitors
Figure
2.2 µF
41, one to each of the four AV
DD
AV
1, AV
DD
DD
(or L2AV
, OV
DD
2, respectively). The AV
DD
DD
, GV
DD
)
System Design Information
DD
, OV
DD
, OV
, and LV
DD
DD
DD
, GV
DD
through a
, GV
pins.
DD
DD
DD
,
pin
DD
DD
,
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