mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 70

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Clocking
19.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
70
0–1
nn
00
01
10
11
00
01
10
11
RCWL[COREPLL]
1
2
Core PLL Configuration
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
CFG_CLKIN_DIV
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
0000
0001
0001
0001
0001
0001
0001
0001
0001
2–5
Table 60
at Reset
Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz.
High
High
High
High
High
High
1
should be considered as reserved.
6
n
0
0
0
0
1
1
1
1
Table 59. CSB Frequency Options for Agent Mode (continued)
Table 60
(PLL off, csb_clk clocks core directly)
shows the encodings for RCWL[COREPLL]. COREPLL values that are
SPMF
0011
0100
0101
0110
0111
1000
Table 60. e300 Core PLL Configuration
core_clk : csb_clk Ratio
PLL bypassed
1.5:1
1.5:1
1.5:1
1.5:1
1:1
1:1
1:1
1:1
Input Clock
csb_clk :
Ratio
10 : 1
12 : 1
14 : 1
16 : 1
6 : 1
8 : 1
NOTE
2
16.67
100
133
166
200
233
266
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
(PLL off, csb_clk clocks core directly)
150
200
250
300
25
33.33
PLL bypassed
VCO Divider
200
266
333
Freescale Semiconductor
2
4
8
8
2
4
8
8
66.67
2
1