mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 32

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Ethernet: Three-Speed Ethernet, MII Management
Figure 16
32
At recommended operating conditions with LV
MDC fall time
Notes:
1. The symbols for timing specifications follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
and t
timing (MD) for the time t
t
relative to the t
is used with the appropriate letter: R (rise) or F (fall).
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
333 MHz, the delay is 58 ns).
MDDVKH
(first two letters of functional block)(reference)(state)(signal)(state)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
Parameter/Condition
shows the MII management AC timing diagram.
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
MDC
(Output)
(Input)
MDIO
MDIO
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
MDC
Table 33. MII Management AC Timing Specifications (continued)
MDC
Figure 16. MII Management Interface Timing Diagram
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
t
MDCH
DD
t
is 3.3 V ± 10% or 2.5 V ± 5%.
MDDVKH
t
MDC
t
MDKHDX
Symbol
t
MDHF
1
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
MDCF
Min
—
t
MDDXKH
t
MDCR
Typ
—
MDKHDX
Max
symbolizes management data
10
Freescale Semiconductor
Unit
ns
for inputs
Notes
—