mpc8349ea Freescale Semiconductor, Inc, mpc8349ea Datasheet - Page 4

• Manufacturer Part Number: mpc8349ea
• Description: Mpc8349ea Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Overview
4
•
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI1, three masters on PCI2
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
— Data encryption standard (DES) execution unit (DEU)
— Advanced encryption standard unit (AESU)
— XOR parity generation accelerator for RAID applications
— ARC four execution unit (AFEU)
— Message digest execution unit (MDEU)
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
MPC8349EA PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits
– ECB, CBC, CCM, and counter (CTR) modes
– Stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– Static and/or dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Freescale Semiconductor