mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 15

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

1.3.5
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock
generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication
factor, output clock divider ratio are all software configurable. The PLL has the following major features:
1.3.6
The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal
connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System. The
Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The
Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI
supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed
region-specific attributes. The calibration EBI supports the following features:
Freescale Semiconductor
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Input clock frequency from 4 MHz to 20 MHz
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in system clock frequencies from
16 MHz to 80 MHz with granularity of 4 MHz or better
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
3 modes of operation
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
Each of the three modes may be run with a crystal oscillator or an external clock reference
Programmable frequency modulation
— Modulation enabled/disabled through software
— Triangle wave modulation up to 100 kHz modulation frequency
— Programmable modulation depth (0% to 2% modulation depth)
— Programmable modulation frequency dependent on reference frequency
Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to
report loss of lock conditions
Clock Quality Module
— detects the quality of the crystal clock and cause interrupt request or system reset if error is detected
— detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system
Programmable interrupt request or system reset on loss of lock
Self-clocked mode (SCM) operation
22-bit address bus (two most significant signals multiplexed with two chip selects)
16-bit data bus
Multiplexed mode with addresses and data signals present on the data lines
Memory controller with support for various memory types:
— Asynchronous/legacy flash and SRAM
— Most standard memories used with the MPC5xx or MPC55xx family
Bus monitor
clock to the crystal clock and causes an interrupt request
FMPLL
Calibration EBI
The calibration EBI must be configured in multiplexed mode when the extended Nexus
trace is used on the VertiCal Calibration System. This is because Nexus signals and address
lines of the calibration bus share the same balls in the calibration package.
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
NOTE
Overview
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