mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 5

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
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High performance e200z335 core processor
— 32-bit Power Architecture Book E programmer’s model
— Variable Length Encoding Enhancements
— Single issue, 32-bit Power Architecture Book E compliant CPU
— In-order execution and retirement
— Precise exception handling
— Branch processing unit
— Load/store unit
— Thirty-two 64-bit general purpose registers (GPRs)
— Memory management unit (MMU) with 8-entry fully-associative translation look-aside buffer (TLB)
— Separate instruction bus and load/store bus
— Vectored interrupt support
— Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt
— Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g.,
— Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt
— New ‘Wait for Interrupt’ instruction, to be used with new low power modes
— Reservation instructions for implementing read-modify-write accesses
— Signal processing extension (SPE) APU
— Floating point
— Long cycle time instructions, except for guarded loads, do not increase interrupt latency
— Extensive system development support through Nexus debug port
Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
– On-chip bypass capacitance
– Selectable slew rate and drive strength
– Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions
– Results in smaller code size
– Dedicated branch address calculation adder
– Branch acceleration using Branch Lookahead Instruction Buffer
– One-cycle load latency
– Fully pipelined
– Big and Little Endian support
– Misaligned access support
– Zero load-to-use pipeline bubbles
exception handler)
power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be
recoverable)
Controller. (Always recoverable)
– Operating on all 32 GPRs that are all extended to 64 bits wide
– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including
– Provides rich array of extended 64-bit loads and stores to/from extended GPRs
– Fully code compatible with e200z6 core
– IEEE 754 compatible with software wrapper
– Scalar single precision in hardware, double precision with software library
– Conversion instructions between single precision floating point and fixed point
– Fully code compatible with e200z6 core
integer vector MAC and MUL operations) (SIMD)
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Overview
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