mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 17

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

1.3.8
The error correction status module provides status information regarding platform memory errors reported by error-correcting
codes.
1.3.9
The MPC5634M provides up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can
be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes the performance of
the flash array to match the CPU architecture and provides single cycle random access to the flash @ 80 MHz. The flash module
interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction
fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module
contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential lines of data from the flash
array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are registered and are forwarded
to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be automatically controlled, and
are restricted to instruction fetch.
The flash memory provides the following features:
1.3.10
The MPC5634M SRAM module provides a general-purpose up to 94 KB memory block. The SRAM controller includes these
features:
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Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword
reads are supported. Only aligned word and doubleword writes are supported.
Fetch Accelerator
— Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the
— Configurable read buffering and line prefetch support
— Four line read buffers (128 bits wide) and a prefetch controller
Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in
parallel for interleaved or pipelined flash array designs
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation
of other memory types
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 128 bits (four words) to accelerate programming
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block
Supports read/write accesses mapped to the SRAM memory from any master
32 KB or 24 KB block powered by separate supply for standby operation
flash up to 80 MHz system clock speed
ECSM
Flash
SRAM
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Overview
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