mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 9
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mpc5632m
Manufacturer Part Number
mpc5632m
Description
Mpc5634m Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC5632M.pdf
(112 pages)
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Freescale Semiconductor
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1.176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
— Double match/capture channels
— Angle clock hardware support
— Nexus Class 1 Debug support
— Enhancements to make DMA and interrupt operation more flexible
— New programmable channel mode, for increased flexibility of channel hardware
— Scheduler priority-passing mechanism can be disabled
— New Watchdog mechanism kills threads over a programmable timeout
— New counter allows microengine load information collection for performance analysis
— Channels 1 and 2 (besides channel 0) can now be selected to control the EAC
— Timebase prescalers are now reset when the GTBE input is negated, guaranteeing synchronization with eMIOS in
— New MISC flag indicates when an SCM signature calculation round is completed. This allows
— New channel TCCEA flag allows continuous capture even after TDLA is set, making it fully compatible with TPU
— New branch condition PRSS tells the pin state at the time when a channel (match or transition)
— MRLEA/B can now be negated independently by microcode
— New Engine Relative address mode allows a function to access SDM address space common to one engine, but
Enhanced queued A/D converter (eQADC)
— Two independent on-chip RSD Cyclic ADCs
— Automatic application of ADC calibration constants
— Up to 34
— Four pairs of differential analog input channels
— Full duplex synchronous serial interface to an external device
all cases
measuring of the average MISC scan period in a real application situation
behavior
service request occurred
distinct between engines
– 8-, 10-, and 12-bit resolution
– Differential conversions
– Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK=7.5 MHz) and 8-bit accuracy at 1 MSample/s
– Differential channels include variable gain amplifier for improved dynamic range (x1; x2; x4)
– Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
– Single-ended signal range from 0 to 5 V
– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
– Provides time stamp information when requested
– Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)
– Supports both right-justified unsigned and signed formats for conversion results
– Temperature sensor to enable measurement of die temperature
– Ability to measure all power supply pins directly
– Provision of reference voltages (25% VREF and 75% VREF) for ADC calibration purposes
– Has a free-running clock for use by the external device
– Supports a 26-bit message length
(ADC_CLK=15 MHz) for differential conversions
(200 kΩ; 100 kΩ; low value of 5 kΩ)
1
input channels available to the two on-chip ADCs
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Overview
9
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