dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 108

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

LSC
LBC
RST
V
GND 11
Symbol
CC 11
7 0 Signal Descriptions
7 5 ELECTRICAL INTERFACE
The Electrical Interface signals comprise all of the clocking power supply and ground pins
7 6 PINOUT SUMMARY
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
106 117
116 128
4 17 34
5 18 33
94 100
88 – 91
57 77
Pin
58 78
101
118
87
86
I O
I
I
I
I
I
Local Symbol Clock 25 MHz clock with a 40 60 duty-cycle Typically generated by the CDD
Local Byte Clock 12 5 MHz clock 50 50 duty-cycle in phase with LSC Typically generated by the
CDD
Master Reset Equivalent to setting the Master Reset bit in the Function Register An asynchronous
input that must be asserted for at least 5 LSC clock cycles When asserted all bi-directional signals
are tri-stated Active low signal
Positive Power Supply 5V
Power Supply Return
Control Bus Data 1
Control Bus Data 2
Control Bus Data 3
Positive Power Supply
Ground
Control Bus Data 4
Control Bus Data 5
Control Bus Data 6
Control Bus Data 7
Control Bus Parity
Source Address I G Transparency
Source Address Transparency
Void Strip
Frame Check Sequence Transparency
Request Claim
Request Beacon
Positive Power Supply
Ground
Request Class 3
(Continued)
Signal Name
TABLE 7-6 Pinout Summary
g
5% relative to GND
108
Description
CBD1
CBD2
CBD3
V
GND
CBD4
CBD5
CBD6
CBD7
CBP
SAIGT
SAT
STRIP
FCST
RQCLM
RQBCN
V
GND
RQRCLS3
Symbol
CC
CC
I O
I O
I O
I O
I O
I O
I O
I O
I O
I
I
I
I
I
I
I
I
I
I
I