dp83261 National Semiconductor Corporation, dp83261 Datasheet - Page 51

• Manufacturer Part Number: dp83261
• Description: Bmac Device Fddi Media Access Controller
• Manufacturer: National Semiconductor Corporation

6 0 Control Information
6 5 MAC PARAMETERS
The MAC Parameters are accessible in the Stop Mode These parameters are also accessible in the Run Mode when the
following conditions are met
Otherwise read and write accesses will cause a command error (bit CCE of the Exception Status Register is set to One) and the
access will not be performed
The MAC Parameters are stored in the MAC Parameter RAM They include the following control information
6 5 1 Individual Addresses
The Ring Engine supports both Long and Short Individual Addresses simultaneously The Station’s Long Address is stored in
registers MLA0 – 5 The Station’s Short Address is stored in register MSA0 – 1
For received frames MLA or MSA is compared with the received DA in order to set the Address recognized Flag (A Flag) and
compared with the received SA in order to set the My Address recognized Flag (M Flag) In transmitted frames MLA or MSA
normally replaces the SA from the frame data stream (exception when SA transparency is used)
Bits MLA(47) and MSA(15) are the most significant bits of the address and are transmitted and received first Bits MLA(0) and
MSA(0) are the least significant bits of the address and are transmitted and received last
MLA and MSA should be valid for at least 12 byte times before the Addressing Mode is enabled and should remain valid for at
least 12 byte times after the Addressing Mode is disabled in order to guarantee proper detection
Bits ELA (Enable Long Addressing) and ESA (Enable Short Addressing) in the Option Register determine the address types that
may be recognized and generated by this MAC
My Long Address
My Long Address (MLA0 – MLA5) represent this station’s long 48-bit address
ACCESS RULES
Note MLA(47) should always be set to 0
My Short Address
My Short Address (MSA0 – MSA1) represent this station’s short 16-bit address
ACCESS RULES
Note MSA(15) should always be set to 0



(PGM0 – 1F) and Fixed Group Map (FGM0 – 1)
a) the MAC Transmitter is in state T0 T1 or T3 and
b) bits ITC and IRR of the Option Register are set to One and
c) bits CLM and BCN of the Function Register are set to Zero
MLA0
MLA1
MLA2
MLA3
MLA4
MLA5
MSA0
MSA1
Individual Addresses My Long Address (MLA0 – 5) and My Short Address (MSA0 – 1)
Group Addresses Group Long Address (GLA0 – 4) and Group Short Address (GSA0) Programmable Group Map
MAC Frame Information Requested Target Token Rotation Time (TREQ0 – 3) and Transmit Beacon Type (TBT0 – 3)
Address
Address
40 – 45h
46 – 47h
MLA(47)
MLA(39)
MLA(31)
MLA(23)
MLA(15)
MSA(15)
MLA(7)
MSA(7)
D7
D7
Stop Mode
Stop Mode
Read
Read
MLA(46)
MLA(38)
MLA(30)
MLA(22)
MLA(14)
MSA(14)
MLA(6)
MSA(6)
D6
D6
(Continued)
Stop Mode
Stop Mode
MLA(45)
MLA(37)
MLA(29)
MLA(21)
MLA(13)
MLA(5)
MSA(13)
Write
Write
MSA(5)
D5
D5
MLA(44)
MLA(36)
MLA(28)
MLA(20)
MLA(12)
MLA(4)
MSA(12)
MSA(4)
D4
D4
51
MLA(43)
MLA(35)
MLA(27)
MLA(19)
MLA(11)
MLA(3)
MSA(11)
MSA(3)
D3
D3
MLA(42)
MLA(34)
MLA(26)
MLA(18)
MLA(10)
MLA(2)
MSA(10)
MSA(2)
D2
D2
MLA(41)
MLA(33)
MLA(25)
MLA(17)
MLA(9)
MLA(1)
MSA(9)
MSA(1)
D1
D1
MLA(40)
MLA(32)
MLA(24)
MLA(16)
MLA(8)
MLA(0)
MSA(8)
MSA(0)
D0
D0