dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 24

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
INTERRUPT CONDITION REGISTER (ICR)
The Interrupt Condition Register records the occurrence of an internal error event the detection of Line State an unsuccessful
write by the Control Bus Interface the expiration of an internal counter or the assertion of one or more of the User Definable
Sense pins
The Interrupt Condition Register will assert the Interrupt pin (INT) when one or more bits within the register are set to 1 and the
corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1
ACCESS RULES
D0
D1
D2
D3
Bit
D7
UDI
ADDRESS
02h
D6
RCB
DPE
CPE
CCR
CWI
Symbol
(Continued)
Always
READ
D5
RCA
PHY REQUEST DATA PARITY ERROR This bit will be set to 1 when
(1) The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register
(CTSR) is set to 1 and
(2) The Transmitter Block detects a parity error in the incoming PHY Request Data
The source of the data can be from the PHY Invalid Bus the Receiver Bus the A Bus or the
B Bus of the Configuration Switch
CONTROL BUS DATA PARITY ERROR This bit will be set to 1 when
(1) The Control Bus Parity Enable pin is asserted (CBPE
(2) The Control Bus Interface detects a parity error in the incoming Control Bus Data
(CBD
CONTROL BUS WRITE COMMAND REJECT This bit will be set to 1 when an attempt to
write into one of the following read-only registers is made
CONDITIONAL WRITE INHIBIT Set to 1 when bits within mentioned registers do not match
bits in compare register This bit ensures that new (i e unread) data is not inadvertently
cleared while old data is being cleared through the Control Bus Interface
This bit is set to 1 to prevent the setting or clearing of any bit within the following registers
when they differ from the value of the corresponding bit in the following registers respectively
This bit must be cleared by software Note that this differs from the BMAC device bit of the
same name
Current Receive State Register (Register 08 CRSR)
Current Noise Count Register (Register 0F CNCR)
Current Noise Prescale Count Register (Register 10 CNPCR)
Current State Count Register (Register 13 CSCR)
Current State Prescale Count Register (Register 14 CSPCR)
Current Link Error Count Register (Register 16 CLECR)
Device ID Register (Register 18 IDR)
Current Injection Count Register (Register 19 CIJCR)
Reserved Register 0 (Register 1E RR0)
Reserved Register 1 (Register 1F RR1)
Interrupt Condition Register (Register 02 ICR)
Current Transmit State Register (Register 04 CTSR)
Receive Condition Register A (Register 09 RCRA)
Receive Condition Register B (Register 0A RCRB)
Interrupt Condition Compare Register (Register 1A ICCR)
Current Transmit State Compare Register (Register 1B CTSCR)
Receive Condition Compare Register A (Register 1C RCCRA)
Receive Condition Compare Register B (Register 1D RCCRB)
k
7 0
D4
LEMT
Conditional
l
WRITE
) during a write cycle
D3
CWI
24
D2
CCR
Description
D1
CPE
e
V
CC
) and
D0
DPE