dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 32

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

D0 D1
D2
D3
D4
5 0 Registers
CURRENT RECEIVE STATE REGISTER (CRSR)
The Current Receive State Register represents the current line state being detected by the Receiver Block Once the Receiver
Block recognizes a new Line State the bits corresponding to the previous line state are cleared and the bits corresponding to
the new line state are set
During the reset process (RST
(LSU) is set to 1)
ACCESS RULES
Bit
D7
RES
ADDRESS
08h
LS0 LS1
LS2
LSU
RES
Symbol
D6
RES
(Continued)
READ
Always
LINE STATE
Block Once the Receiver Block recognizes a new line state the bits corresponding to the previous
line state are cleared and the bits corresponding to the new line state are set
LINE STATE UNKNOWN The Receiver Block has not detected the minimum conditions to enter a
known line state When the Line State Unknown bit is set LS
known line state
RESERVED Reserved for future use The reserved bit is set to 0
Note Users are discouraged from using this bit An attempt to write into this bit will cause the PLAYER device to ignore
the Control Bus write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition
Register (ICR) to 1
D5
RES
e
GND) the Receiver Block is forced to Line State Unknown (i e the Line State Unknown bit
k
LS2
0 1 2
0
0
0
0
1
1
1
1
WRITE
Write Reject
D4
RES
l
These bits represent the current Line State being detected by the Receiver
LS1
0
0
1
1
0
0
1
1
D3
LSU
32
LS0
Description
D2
LS2
0
1
0
1
0
1
0
1
Active Line State (ALS) Received a JK
symbol pair (11000 10001) and possibly
followed by data symbols
Idle Line State (ILS) Received a minimum
of two consecutive Idle symbol pairs (11111
11111)
No Signal Detect (NSD) The Signal Detect
pin (TTLSD) has been deasserted indicating
that the Clock Recovery Device is not
receiving data from the Fiber Optic Receiver
Reserved Reserved for future use
Master Line State (MLS) Received a
minimum of 8 consecutive Halt-Quiet symbol
pairs (00100 00000)
Halt Line State (HLS) Received a minimum
of 8 consecutive Halt symbol pairs (00100
00100)
Quiet Line State (QLS) Received a
minimum of 8 consecutive Quiet symbol pairs
(00000 00000)
Noise Line State (NLS) Detected a
minimum of 16 noise events Refer to the
Receiver Block for further information on
noise events
D1
LS1
k
2 0
l
represent the most recently
D0
LS0