dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 34

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
RECEIVE CONDITION REGISTER A (RCRA)
The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block
When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line
States are not cleared by the PLAYER device thereby maintaining a record of the Line States detected
The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is
also set to 1
ACCESS RULES
D0
D1
D2
D3
D4
D5
D6
D7
D7
LSUPI
ADDRESS
Bit
09h
D6
LSC
(Continued)
NSD
QLS
HLS
MLS
NLS
NT
LSC
LSUPI
Symbol
READ
Always
D5
NT
WRITE
Conditional
D4
NLS
NO SIGNAL DETECT Indicates that the Signal Detect pin (TTLSD) has been
deasserted and that the Clock Recovery Device is not receiving data from the
Fiber Optic Receiver
QUIET LINE STATE Received a minimum of eight consecutive Quiet symbol
pairs (00000 00000)
HALT LINE STATE Received a minimum of eight consecutive Halt symbol
pairs (00100 00100)
MASTER LINE STATE Received a minimum of eight consecutive Halt-Quiet
symbol pairs (00100 00000)
NOISE LINE STATE Detected a minimum of sixteen noise events
NOISE THRESHOLD This bit is set to 1 when the internal Noise Counter
reaches 0 It will remain set until a value equal to or greater than one is
loaded into the Noise Threshold Register or Noise Prescale Threshold
Register
During the reset process (i e RST
initialized to 0 the Noise Threshold bit will be set to 1
LINE STATE CHANGE A line state change has been detected
LINE STATE UNKNOWN
detected the minimum conditions to enter a known line state
In addition the most recently known line state was one of the following line
states No Signal Detect Quiet Line State Halt Line State Master Line State
or Noise Line State
D3
MLS
34
D2
HLS
PHY INVALID The Receiver Block has not
Description
e
D1
QLS
GND) since the Noise Counter is
D0
NSD