dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 54

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
RECEIVE CONDITION COMPARISON REGISTER B (RCCRB)
The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface
The current state of RCRB is automatically written into the Receive Condition Comparison Register B (i e RCCRB
during a Control Bus Interface read-cycle RCRB
During a Control Bus Interface write-cycle the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs
from the value of the corresponding bit in the Receive Condition Comparison Register B
ACCESS RULES
RESERVED REGISTER 0 (RR0) ADDRESS 1Eh DO NOT USE
RESERVED REGISTER 1 (RR1) ADDRESS 1Fh DO NOT USE
D0
D1
D2
D3
D4
D5
D6
D7
Bit
D7
RESC
ADDRESS
1Dh
D6
SILSC
ILSC
STC
ALSC
LSUPVC
CSEC
EBOUC
SILSC
RESC
Symbol
(Continued)
Always
READ
D5
EBOUC
IDLE LINE STATE COMPARISON The comparison bit for the Idle State bit (ILS) of the
Receive Condition Register B (RCRB)
STATE THRESHOLD COMPARISON The comparison bit for the State Threshold bit
(ST) of the Receive Condition Register B (RCRB)
ACTIVE LINE STATE COMPARISON The comparison bit for the Active Line State bit
(ALS) of the Receive Condition Register B (RCRB)
LINE STATE UNKNOWN
State Unknown
CASCADE SYNCHRONIZATION ERROR COMPARISON The comparison bit for the
Cascade Synchronization Error bit (CSE) of the Receive Condition Register B (RCRB)
ELASTICITY BUFFER OVERFLOW UNDERFLOW COMPARISON The comparison bit
for the Elasticity Buffer Overflow Underflow bit (EBOU) of the Receive Condition
Register B (RCRB)
SUPER IDLE LINE STATE COMPARISON The comparison bit for the Super Idle Line
State bit (SILS) of the Receive Condition Register B (RCRB)
RESERVED COMPARISON The comparison bit for the Reserved bit (RES) of the
Receive Condition Register B (RCRB)
D4
CSEC
WRITE
Always
PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB)
D3
LSUPVC
54
PHY VALID COMPARISON The comparison bit for the Line
D2
ALSC
Description
D1
STC
D0
ILSC
e
RCRB)