dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 61

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

Symbol
CE
R W
ACK
INT
CBA4
CBA3
CBA2
CBA1
CBA0
CBPE
CBP
CBD7
CBD6
CBD5
CBD4
CBD3
CBD2
CBD1
CBD0
6 0 Pin Descriptions
CONTROL BUS INTERFACE
The Control Bus Interface consists of I O signals used to connect the PLAYER device to Station Management (SMT)
The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor It provides
access to 32 8-bit internal registers
Refer to Figure 22 Control Bus Timing Diagram for more information
Pin No
73
72
75
74
80
79
78
77
76
13
83
82
9
8
7
5
4
2
1
I O
I O
I O
O
O
I
I
I
I
(Continued)
Chip Enable An active-low TTL input signal which enables the Control Bus port for a read
or write cycle R W CBA
Read E Write A TTL input signal which indicates a read Control Bus cycle (R W
a write Control Bus cycle (R W
valid until ACK becomes low
completion of a read or write cycle
During a read cycle CBD
During a write cycle a microprocessor must hold CBD
Once ACK is low it will remain low as long as CE remains low (CE
condition has occurred The Interrupt Condition Register (ICR) should be read in order to
find out the source of the interrupt Interrupts can be masked through the use of the
Interrupt Condition Mask Register (ICMR)
Control Bus Address TTL input signals used to select the address of the register to be
read or written
CBA4 is the most significant bit (MSB) CBA0 is the least significant bit (LSB) of the address
signals
These signals must be valid when CE is low and held valid until ACK becomes low
Control Bus Parity Enable A TTL input signal which during write cycles will enable or
disable the Control Bus parity checker Note that the Control Bus will always generate
parity during read cycles regardless of the state of this signal
Control Bus Parity A bidirectional TTL signal representing odd parity for the Control Bus
data (CBD
During a read cycle the signal is held valid by the PLAYER device as long as ACK is low
During a write cycle the signal must be valid when CE is low and must be held valid until
ACK becomes low If incorrect parity is used during a write cycle the PLAYER device will
inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt
Condition Register (ICR)
Control Bus Data Bidirectional TTL signals containing the data to be read from or written
to a register
During a read cycle the signal is held valid by the PLAYER device as long as ACK is low
During a write cycle the signal must be valid when CE is low and must be held valid until
ACK becomes low
E Acknowledge An active low TTL open drain output signal which indicates the
E Interrupt An active low open drain TTL output signal indicating that an interrupt
k
7 0
l
)
k
k
61
4 0
7 0
l
l
e
are valid as long as ACK is low (ACK
CBP and CBD
0) This signal must be valid when CE is low and held
Description
k
7 0
l
k
must be valid at the time CE is low
7 0
l
valid until ACK becomes low
e
0)
e
0)
e
1) or