dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 37

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
RECEIVE CONDITION MASK REGISTER B (RCMRB)
The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt
The Receiver Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1
Since this register is cleared (i e set to 0) during the reset process all interrupts are initially masked
ACCESS RULES
D0
D1
D2
D3
D4
D5
D6
D7
D7
RES
ADDRESS
Bit
0Ch
D6
SILSM
(Continued)
ILSM
STM
ALSM
LSUPVM
CSEM
EBOUM
SILSM
RESM
Symbol
READ
Always
D5
EBOUM
D4
CSEM
WRITE
Always
IDLE LINE STATE MASK The mask bit for the Idle Line State bit (ILS) of the
Receive Condition Register B (RCRB)
STATE THRESHOLD MASK The mask bit of the State Threshold bit (ST) of
the Receive Condition Register B (RCRB)
ACTIVE LINE STATE MASK The mask bit for the Active Line State bit (ALS)
of the Receive Condition Register B (RCRB)
LINE STATE UNKNOWN
State Unknown
(RCRB)
CASCADE SYNCHRONIZATION ERROR MASK The mask bit for the
Cascade Synchronization Error bit (CSE) of the Receive Condition Register B
(RCRB)
ELASTICITY BUFFER OVERFLOW UNDERFLOW MASK The mask bit for
the Elasticity Buffer Overflow Underflow bit (EBOU) of the Receive Condition
Register B (RCRB)
SUPER IDLE LINE STATE MASK The mask bit for the Super Idle Line State
bit (SILS) of the Receive Condition Register B (RCRB)
RESERVED MASK The mask bit for the Reserved bit (RES) of the Receive
Condition Register B (RCRB)
D3
LSUPVM
37
PHY Valid bit (LSUPV) of the Receive Condition Register B
D2
ALSM
PHY VALID MASK The mask bit for the Line
Description
D1
STM
D0
ILSM