w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 47

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

10.11 Data Bus Buffer 1 Address High Register (DBB1ADDH)
10.12 Hardware GATEA20 and KBRESET and Port 92h Support
10.13 Advance Keyboard Controller Register (AKBCTRL)
These two registers are only available in LPC mode, which be used to specify the DBB1 base I/O
address. Then the available I/O ports are at base and base+4h.
Default is {00h, 62h}, so available decode address for DBB1 are 62h and 66h.
Bit 7-3: Reserved
Bit 2: = 0: The handshake mode of PS2 is disable. (Auto drive PS2 CLK Low for 100us after start
When the handshake mode of PS2 is enabling. The TR bit (BIT 0) of PS2CON is automatically set
high at the following conditions.
1:The RDATA_RDY bit (bit 0) of PS2STS of this channel is set
2:The START_DEC bit (bit 6) of PS2STS of the other channel is set
PS: The priority of three PS2 interface is
Bit 1: = 0: The default value is 0 or last D1 command set when the HGA20 enable
Bit 0: The default value for HGA20.
ASFR address 0x05
Default value
The Winbond keyboard controller implements a hardware control logic to speed-up GATEA20 and
KBRESET. This control logic is controlled by KBCTRL register as follows:
ASFR address 0x08
Default value
1: P1PS2
2: P2PS2
3: P3PS2
= 1: The default value is according to the AKBCTRL bit 0 when the HGA20 enable
=1: The handshake mode of PS2 is enable. (Auto drive PS2 CLK Low for 100us after start
bit received.)
bit received.)
0x00
0x00
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W83L950D